Texas Instruments TMS570LC4357 - Page 68

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SPNU563A–March 2018
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List of Figures
34-33. eQEP Decoder Control Register (QDECCTL) [offset = 2Ah]...................................................... 1985
34-34. eQEP Position-Compare Control Register (QPOSCTL) [offset = 2Ch] .......................................... 1986
34-35. eQEP Capture Control Register (QCAPCTL) [offset = 2Eh]....................................................... 1987
34-36. eQEP Interrupt Flag Register (QFLG) [offset = 30h] ............................................................... 1988
34-37. eQEP Interrupt Enable Register (QEINT) [offset = 32h] ........................................................... 1989
34-38. eQEP Interrupt Force Register (QFRC) [offset = 34h] ............................................................. 1990
34-39. eQEP Interrupt Clear Register (QCLR) [offset = 36h].............................................................. 1991
34-40. eQEP Capture Timer Register (QCTMR) [offset = 38h]............................................................ 1992
34-41. eQEP Status Register (QEPSTS) [offset = 3Ah].................................................................... 1993
34-42. eQEP Capture Timer Latch Register (QCTMRLAT) [offset = 3Ch]............................................... 1994
34-43. eQEP Capture Period Register (QCPRD) [offset = 3Eh] .......................................................... 1994
34-44. eQEP Capture Period Latch Register (QCPRDLAT) [offset = 42h] .............................................. 1994
35-1. Multiple ePWM Modules................................................................................................ 1997
35-2. Submodules and Signal Connections for an ePWM Module ...................................................... 1998
35-3. Time-Base Submodule Block Diagram............................................................................... 2002
35-4. Time-Base Submodule Signals and Registers ...................................................................... 2003
35-5. Time-Base Frequency and Period .................................................................................... 2005
35-6. Time-Base Counter Synchronization Scheme....................................................................... 2006
35-7. Time-Base Up-Count Mode Waveforms ............................................................................. 2008
35-8. Time-Base Down-Count Mode Waveforms.......................................................................... 2009
35-9. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event... 2009
35-10. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ...... 2010
35-11. Counter-Compare Submodule......................................................................................... 2010
35-12. Detailed View of the Counter-Compare Submodule................................................................ 2011
35-13. Counter-Compare Event Waveforms in Up-Count Mode .......................................................... 2013
35-14. Counter-Compare Events in Down-Count Mode.................................................................... 2013
35-15. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event ................................................................................................. 2014
35-16. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ..................................................................................................................... 2014
35-17. Action-Qualifier Submodule............................................................................................ 2015
35-18. Action-Qualifier Submodule Inputs and Outputs .................................................................... 2016
35-19. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ......................................... 2017
35-20. Up-Down-Count Mode Symmetrical Waveform ..................................................................... 2020
35-21. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High................................................................................................. 2021
35-22. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 2022
35-23. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 2023
35-24. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low................................................................................................ 2025
35-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary.......................................................................................... 2026
35-26. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low........................................................................................................................ 2027
35-27. Dead_Band Submodule ................................................................................................ 2028
35-28. Configuration Options for the Dead-Band Submodule ............................................................. 2029
35-29. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 2031
35-30. PWM-Chopper Submodule ............................................................................................ 2033
35-31. PWM-Chopper Submodule Operational Details..................................................................... 2034
35-32. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only............................... 2034