Texas Instruments TMS570LC4357 - Page 69

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SPNU563A–March 2018
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List of Figures
35-33. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses...... 2035
35-34. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses..................................................................................................................... 2036
35-35. Trip-Zone Submodule................................................................................................... 2037
35-36. Trip-Zone Submodule Mode Control Logic .......................................................................... 2041
35-37. Trip-Zone Submodule Interrupt Logic................................................................................. 2042
35-38. Event-Trigger Submodule .............................................................................................. 2043
35-39. Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion....................................... 2044
35-40. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 2045
35-41. Event-Trigger Interrupt Generator..................................................................................... 2047
35-42. Event-Trigger SOCA Pulse Generator ............................................................................... 2047
35-43. Event-Trigger SOCB Pulse Generator ............................................................................... 2048
35-44. Digital-Compare Submodule High-Level Block Diagram........................................................... 2048
35-45. DCAEVT1 Event Triggering............................................................................................ 2051
35-46. DCAEVT2 Event Triggering............................................................................................ 2051
35-47. DCBEVT1 Event Triggering............................................................................................ 2052
35-48. DCBEVT2 Event Triggering............................................................................................ 2052
35-49. Event Filtering ........................................................................................................... 2053
35-50. Blanking Window Timing Diagram .................................................................................... 2054
35-51. Simplified ePWM Module............................................................................................... 2055
35-52. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ..................................... 2056
35-53. Control of Four Buck Stages. Here F
PWM1
≠ F
PWM2
≠ F
PWM3
≠ F
PWM4
.................................................. 2057
35-54. Buck Waveforms for (Note: Only three bucks shown here) ....................................................... 2058
35-55. Control of Four Buck Stages. (Note: F
PWM2
= N x F
PWM1
)............................................................ 2060
35-56. Buck Waveforms for (Note: F
PWM2
= F
PWM1)
)........................................................................... 2061
35-57. Control of Two Half-H Bridge Stages (F
PWM2
= N x F
PWM1
).......................................................... 2063
35-58. Half-H Bridge Waveforms for (Note: Here F
PWM2
= F
PWM1
).......................................................... 2064
35-59. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................. 2066
35-60. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ..................................................... 2067
35-61. Configuring Two PWM Modules for Phase Control................................................................. 2068
35-62. Timing Waveforms Associated With Phase Control Between 2 Modules ....................................... 2069
35-63. Time-Base Status Register (TBSTS) [offset = 00h]................................................................. 2071
35-64. Time-Base Control Register (TBCTL) [offset = 02h]................................................................ 2072
35-65. Time-Base Phase Register (TBPHS) [offset = 04h] ................................................................ 2074
35-66. Time-Base Period Register (TBPRD) [offset = 08h]................................................................ 2074
35-67. Time-Base Counter Register (TBCTR) [offset = 0Ah] .............................................................. 2074
35-68. Counter-Compare Control Register (CMPCTL) [offset = 0Ch] .................................................... 2075
35-69. Counter-Compare A Register (CMPA) [offset = 10h]............................................................... 2076
35-70. Counter-Compare B Register (CMPB) [offset = 16h]............................................................... 2077
35-71. Action-Qualifier Output A Control Register (AQCTLA) [offset = 14h] ............................................ 2078
35-72. Action-Qualifier Software Force Register (AQSFRC) [offset = 18h].............................................. 2079
35-73. Action-Qualifier Output B Control Register (AQCTLB) [offset = 1Ah] ............................................ 2080
35-74. Action-Qualifier Continuous Software Force Register (AQCSFRC) [offset = 1Eh] ............................. 2081
35-75. Dead-Band Generator Control Register (DBCTL) [offset = 1Ch] ................................................. 2082
35-76. Dead-Band Generator Falling Edge Delay Register (DBFED) [offset = 20h] ................................... 2084
35-77. Dead-Band Generator Rising Edge Delay Register (DBRED) [offset = 22h].................................... 2084
35-78. Trip Zone Digital Compare Event Select Register (TZDCSEL) [offset = 24h]................................... 2085
35-79. Trip-Zone Select Register (TZSEL) [offset = 26h] .................................................................. 2086
35-80. Trip-Zone Enable Interrupt Register (TZEINT) [offset = 28h]...................................................... 2088