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SPNU563A–March 2018
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List of Figures
2-95. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) (offset = ACh) ................................... 236
2-96. Debug Frame Powerdown Set Register (PDPWRDWNSET) (offset = C0h) ..................................... 236
2-97. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) (offset = C4h)................................... 237
2-98. MasterID Protection Write Enable Register (MSTIDWRENA) (offset = 200h).................................... 237
2-99. MasterID Enable Register (MSTIDENA) (offset = 204h) ............................................................ 238
2-100. MasterID Diagnostic Control Register (MSTIDDIAGCTRL) (offset = 208h)....................................... 239
2-101. Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L) (offset = 300h) ........................... 240
2-102. Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H) (offset = 304h) .......................... 242
2-103. Peripheral Frame n MasterID Protection Register_L/H (PSnMSTID_L/H) (offset = 308h-3FCh) .............. 243
2-104. Privileged Peripheral Frame 0 MasterID Protection Register_L (PPS0MSTID_L) (offset = 400h)............. 244
2-105. Privileged Peripheral Frame 0 MasterID Protection Register_H (PPS0MSTID_H) (offset = 404h)............ 245
2-106. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H) (offset = 408h-43Ch) 246
2-107. Privileged Peripheral Extended Frame 0 MasterID Protection Register_L (PPSE0MSTID_L) (offset =
440h) ....................................................................................................................... 247
2-108. Privileged Peripheral Extended Frame 0 MasterID Protection Register_H (PPSE0MSTID_H) (offset =
444h) ....................................................................................................................... 248
2-109. Privileged Peripheral Extended Frame n MasterID Protection Register_L/H (PPSEnMSTID_L/H) (offset =
448h-53Ch) ................................................................................................................ 249
2-110. Peripheral Memory Frame MasterID Protection Register (PCSnMSTID) (offset = 540h-5BCh) ............... 250
2-111. Privileged Peripheral Memory Frame MasterID Protection Register (PPCSnMSTID) (offset = 5C0h-5DCh) 251
3-1. System Level Block Diagram............................................................................................ 254
3-2. SCM Block Diagram...................................................................................................... 255
3-3. Timeout Threshold Compare............................................................................................ 256
3-4. SCM Control Block ....................................................................................................... 256
3-5. SCM REVID Register (SCMREVID) [offset = 00h]................................................................... 260
3-6. SCM Control Register (SCMCNTRL) [offset = 04h].................................................................. 261
3-7. SCM Compare Threshold Counter Register (SCMTHRESHOLD) [offset = 08h] ................................ 262
3-8. SCM Initiator Error0 Status Register (SCMIAERR0STAT) [offset = 10h] ......................................... 263
3-9. SCM Initiator Error1 Status Register (SCMIAERR1STAT) [offset = 14h] ......................................... 263
3-10. SCM Initiator Active Status Register (SCMIASTAT) [offset = 18h] ................................................ 264
3-11. SCM Target Active Status Register (SCMTASTAT) [offset = 20h]................................................. 264
4-1. Interconnect Block Diagram ............................................................................................. 266
4-2. SDC Status Register (SDC_STATUS) (offset = 00h)................................................................ 273
4-3. SDC Control Register (SDC_STATUS) (offset = 04h)............................................................... 274
4-4. Error Generic Parity Register (ERR_GENERIC_PARITY) (offset = 08h) ......................................... 274
4-5. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) (offset = 0Ch) ....................... 275
4-6. Error Transaction ID Register (ERR_TRANS_ID) (offset = 10h)................................................... 275
4-7. Error Transaction Signature Register (ERR_TRANS_SIGNATURE) (offset = 14h) ............................. 276
4-8. Error Transaction Type Register (ERR_TRANS_TYPE) (offset = 18h) ........................................... 276
4-9. Error User Parity Register (ERR_USER_PARITY) (offset = 1Ch) ................................................. 277
4-10. Slave Error Unexpected Master ID Register (SERR_UNEXPECTED_MID) (offset = 20h)..................... 277
4-11. Slave Error Address Decode Register (SERR_ADDR_DECODE) (offset = 24h)................................ 278
4-12. Slave Error User Parity Register (SERR_USER_PARITY) (offset = 28h) ........................................ 278
5-1. PMM Block Diagram...................................................................................................... 281
5-2. Core Power Domains..................................................................................................... 282
5-3. Logic Power Domain Control Register (LOGICPDPWRCTRL0) (offset = 00h) .................................. 286
5-4. Logic Power Domain Control Register (LOGICPDPWRCTRL1) (offset = 04h) .................................. 287
5-5. Power Domain Clock Disable Register (PDCLKDISREG) (offset = 20h) ......................................... 288
5-6. Power Domain Clock Disable Set Register (PDCLKDISSETREG) (offset = 24h) ............................... 289
5-7. Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) (offset = 28h)............................. 290
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