Texas Instruments TMS570LC4357

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99
SPNU563A–March 2018
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List of Tables
32-36. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions....................................... 1877
32-37. MDIO User Access Register 1 (USERACCESS1) Field Descriptions............................................ 1878
32-38. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions....................................... 1879
32-39. Ethernet Media Access Controller (EMAC) Registers.............................................................. 1880
32-40. Transmit Revision ID Register (TXREVID) Field Descriptions .................................................... 1883
32-41. Transmit Control Register (TXCONTROL) Field Descriptions .................................................... 1883
32-42. Transmit Teardown Register (TXTEARDOWN) Field Descriptions............................................... 1884
32-43. Receive Revision ID Register (RXREVID) Field Descriptions..................................................... 1884
32-44. Receive Control Register (RXCONTROL) Field Descriptions..................................................... 1885
32-45. Receive Teardown Register (RXTEARDOWN) Field Descriptions ............................................... 1885
32-46. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions....................... 1886
32-47. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ..................... 1887
32-48. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions................................... 1888
32-49. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions............................. 1889
32-50. MAC Input Vector Register (MACINVECTOR) Field Descriptions................................................ 1890
32-51. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions ................................ 1891
32-52. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ....................... 1892
32-53. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions...................... 1893
32-54. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ................................... 1894
32-55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................. 1895
32-56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions......................... 1896
32-57. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions ....................... 1896
32-58. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions..................................... 1897
32-59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions............................... 1897
32-60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions.............................................................................................................. 1898
32-61. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions................................... 1900
32-62. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions...................................... 1901
32-63. Receive Maximum Length Register (RXMAXLEN) Field Descriptions........................................... 1901
32-64. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ...................................... 1902
32-65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions...... 1902
32-66. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............. 1903
32-67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions .................... 1903
32-68. MAC Control Register (MACCONTROL) Field Descriptions ...................................................... 1904
32-69. MAC Status Register (MACSTATUS) Field Descriptions.......................................................... 1906
32-70. Emulation Control Register (EMCONTROL) Field Descriptions .................................................. 1908
32-71. FIFO Control Register (FIFOCONTROL) Field Descriptions ...................................................... 1908
32-72. MAC Configuration Register (MACCONFIG) Field Descriptions.................................................. 1909
32-73. Soft Reset Register (SOFTRESET) Field Descriptions ............................................................ 1909
32-74. MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions........................... 1910
32-75. MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions ........................... 1910
32-76. MAC Hash Address Register 1 (MACHASH1) Field Descriptions................................................ 1911
32-77. MAC Hash Address Register 2 (MACHASH2) Field Descriptions................................................ 1911
32-78. Back Off Test Register (BOFFTEST) Field Descriptions .......................................................... 1912
32-79. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ................................... 1912
32-80. Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................. 1913
32-81. Transmit Pause Timer Register (TXPAUSE) Field Descriptions.................................................. 1913
32-82. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions.......................................... 1914
32-83. MAC Address High Bytes Register (MACADDRHI) Field Descriptions .......................................... 1915