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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
List of Tables
31-24. I2C Peripheral ID Register 2 (I2CPID2) Field Descriptions........................................................ 1795
31-25. I2C DMA Control Register (I2CDMACR) Field Descriptions ...................................................... 1796
31-26. I2C Pin Function Register (I2CPFNC) Field Descriptions ......................................................... 1796
31-27. I2C Pin Direction Register (I2CPDIR) Field Descriptions .......................................................... 1797
31-28. I2C Data Input Register (I2CDIN) Field Descriptions............................................................... 1797
31-29. I2C Data Output Register (I2CDOUT) Field Descriptions.......................................................... 1798
31-30. I2C Data Set Register (I2CDSET) Field Description ............................................................... 1798
31-31. I2C Data Clear Register (I2CDSET) Field Descriptions............................................................ 1799
31-32. I2C Pin Open Drain Register (I2CPDR) Field Descriptions........................................................ 1799
31-33. I2C Pull Disable Register (I2CPDIS) Field Descriptions ........................................................... 1800
31-34. I2C Pull Select Register (I2CPSEL) Field Descriptions ............................................................ 1800
31-35. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ........................................... 1801
31-36. I2C Pins Slew Rate Select Register (I2CSRS) Field Descriptions................................................ 1801
32-1. EMAC and MDIO Signals for MII Interface .......................................................................... 1808
32-2. EMAC and MDIO Signals for RMII Interface ........................................................................ 1809
32-3. MDIO Multiplexing Control ............................................................................................. 1810
32-4. MII/RMII Multiplexing Control .......................................................................................... 1810
32-5. Ethernet Frame Description............................................................................................ 1811
32-6. Basic Descriptor Description........................................................................................... 1813
32-7. Receive Frame Treatment Summary................................................................................. 1842
32-8. Middle of Frame Overrun Treatment ................................................................................. 1843
32-9. Emulation Control ....................................................................................................... 1853
32-10. EMAC Control Module Registers...................................................................................... 1854
32-11. EMAC Control Module Revision ID Register (REVID) Field Descriptions ....................................... 1855
32-12. EMAC Control Module Software Reset Register (SOFTRESET)................................................. 1855
32-13. EMAC Control Module Interrupt Control Register (INTCONTROL) .............................................. 1856
32-14. EMAC Control Module Receive Threshold Interrupt Enable Register (C0RXTHRESHEN)................... 1857
32-15. EMAC Control Module Receive Interrupt Enable Register (C0RXEN)........................................... 1858
32-16. EMAC Control Module Transmit Interrupt Enable Register (C0TXEN) .......................................... 1859
32-17. EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN) ................................ 1860
32-18. EMAC Control Module Receive Threshold Interrupt Status Register (C0RXTHRESHSTAT) ................ 1861
32-19. EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) ........................................ 1862
32-20. EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) ........................................ 1863
32-21. EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT) .............................. 1864
32-22. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX)............................. 1865
32-23. EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) ............................ 1866
32-24. Management Data Input/Output (MDIO) Registers ................................................................. 1867
32-25. MDIO Revision ID Register (REVID) Field Descriptions ........................................................... 1867
32-26. MDIO Control Register (CONTROL) Field Descriptions ........................................................... 1868
32-27. PHY Acknowledge Status Register (ALIVE) Field Descriptions .................................................. 1869
32-28. PHY Link Status Register (LINK) Field Descriptions ............................................................... 1869
32-29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions .............. 1870
32-30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions............. 1871
32-31. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ..... 1872
32-32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions.... 1873
32-33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .. 1874
32-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions.............................................................................................................. 1875
32-35. MDIO User Access Register 0 (USERACCESS0) Field Descriptions............................................ 1876