Texas Instruments TMS570LC4357 - Page 97

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SPNU563A–March 2018
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List of Tables
30-8. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions........................................... 1742
30-9. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions .................................... 1743
30-10. SCI Flags Register (SCIFLR) Field Descriptions.................................................................... 1745
30-11. SCI Receiver Status Flags ............................................................................................ 1748
30-12. SCI Transmitter Status Flags ......................................................................................... 1748
30-13. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................ 1749
30-14. SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................ 1749
30-15. SCI Format Control Register (SCIFORMAT) Field Descriptions.................................................. 1750
30-16. Baud Rate Selection Register (BRS) Field Descriptions .......................................................... 1751
30-17. Comparative Baud Values for Different P Values, Asynchronous Mode ........................................ 1751
30-18. Receiver Emulation Data Buffer (SCIED) Field Descriptions...................................................... 1752
30-19. Receiver Data Buffer (SCIRD) Field Descriptions .................................................................. 1752
30-20. Transmit Data Buffer Register (SCITD) Field Descriptions........................................................ 1753
30-21. SCI Pin I/O Control Register 0 (SCIPIO0) Field Descriptions ..................................................... 1753
30-22. SCI Pin I/O Control Register 1 (SCIPIO1) Field Descriptions ..................................................... 1754
30-23. SCITX Pin Control ...................................................................................................... 1754
30-24. SCIRX Pin Control ..................................................................................................... 1754
30-25. SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions .................................................... 1755
30-26. SCI Pin I/O Control Register 3 (SCIPIO3) Field Descriptions .................................................... 1756
30-27. SCI Pin I/O Control Register 4 (SCIPIO4) Field Descriptions .................................................... 1757
30-28. SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions .................................................... 1758
30-29. SCI Pin I/O Control Register 6 (SCIPIO6) Field Descriptions ..................................................... 1759
30-30. SCI Pin I/O Control Register 7 (SCIPIO7) Field Descriptions ..................................................... 1760
30-31. SCI Pin I/O Control Register 8 (SCIPIO8) Field Descriptions .................................................... 1760
30-32. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions ........................................... 1761
30-33. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ........................................... 1764
31-1. Ways to Generate a NACK Bit ........................................................................................ 1773
31-2. Interrupt Requests Generated by I2C Module....................................................................... 1778
31-3. I2C Control Registers................................................................................................... 1781
31-4. I2C Own Address Manager Register (I2COAR) Field Descriptions .............................................. 1782
31-5. Correct Mode for OA Bits .............................................................................................. 1782
31-6. I2C Interrupt Mask Register (I2CIMR) Field Descriptions.......................................................... 1783
31-7. I2C Status Register (I2CSTR) Field Descriptions................................................................... 1784
31-8. I2C Clock Divider Low Register (I2CCKL) Field Descriptions..................................................... 1787
31-9. I2C Clock Control High Register (I2CCKH) Field Descriptions ................................................... 1787
31-10. I2C Data Count Register (I2CCNT) Field Descriptions............................................................. 1788
31-11. I2C Data Receive Register (I2CDRR) Field Descriptions.......................................................... 1788
31-12. I2C Slave Address Register (I2CSAR) Field Descriptions......................................................... 1789
31-13. Correct Mode for SA Bits............................................................................................... 1789
31-14. I2C Data Transmit Register (I2CDXR) Field Descriptions ......................................................... 1789
31-15. I2C Mode Register (I2CMDR) Field Descriptions................................................................... 1790
31-16. I2C Module Condition, Bus Activity, and Mode...................................................................... 1792
31-17. I2C Module Operating Modes ......................................................................................... 1792
31-18. Number of Bits Sent on Bus ........................................................................................... 1792
31-19. I2C Interrupt Vector Register (I2CIVR) Field Descriptions......................................................... 1793
31-20. Interrupt Codes for INTCODE Bits.................................................................................... 1793
31-21. I2C Extended Mode Register (I2CEMDR) Field Descriptions..................................................... 1794
31-22. I2C Prescale Register (I2CPSC) Field Descriptions................................................................ 1794
31-23. I2C Peripheral ID Register 1 (I2CPID1) Field Descriptions........................................................ 1795