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SPRUH91D–March 2013–Revised September 2016
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Multichannel Audio Serial Port (McASP)
24.0.21.4 TDM Sequencer
There are separate TDM sequencers for the transmit section and the receive section. Each TDM
sequencer keeps track of the slot count. In addition, the TDM sequencer checks the bits of (R/X)TDM and
determines if the McASP should receive/transmit in that time slot.
If the McASP should participate (transmit/receive bit is active) in the time slot, the McASP functions
normally. If the McASP should not participate (transmit/receive bit is inactive) in the time slot, no transfers
between the XRBUF and XRSR registers in the serializer would occur during that time slot. In addition, the
serializers programmed as transmitters place their data output pins in a predetermined state (logic low,
high, or high impedance) as programmed by each serializer control register (SRCTL). Refer also to
Section 24.0.21.2.2 for details on how DMA event or interrupt generations are handled during inactive time
slots in TDM mode.
The receive TDM sequencer is controlled by register RTDM and reports current receive slot to RSLOT.
The transmit TDM sequencer is controlled by register XTDM and reports current transmit slot to XSLOT.
24.0.21.5 Clock Check Circuit
A common source of error in audio systems is a serial clock failure due to instabilities in the off-chip DIR
circuit. To detect a clock error quickly, a clock-check circuit is included in the McASP for both transmit and
receive clocks, since both may be sourced from off chip.
The clock check circuit can detect and recover from transmit and receive clock failures. See
Section 24.0.21.6.6 for implementation and programming details.
24.0.21.6 Pin Function Control
All McASP pins except AMUTEIN are bidirectional input/output pins. In addition, these bidirectional pins
function either as McASP or general-purpose I/O (GPIO) pins. The following registers control the pin
functions:
• Pin function register (PFUNC): selects pin to function as McASP or GPIO
• Pin direction register (PDIR): selects pin to be input or output
• Pin data input register (PDIN): shows data input at the pin
• Pin data output register (PDOUT): data to be output at the pin if the pin is configured as GPIO output
(PFUNC[n] = 1 and PDIR[n] = 1). Not applicable when the pin is configured as McASP pin
(PFUNC[n] = 0).
• Pin data set register (PDSET): alias of PDOUT. Writing a 1 to PDSET[n] sets the respective PDOUT[n]
to 1. Writing a 0 has no effect. Applicable only when the pin is configured as GPIO output
(PFUNC[n] = 1 and PDIR[n] = 1).
• Pin data clear register (PDCLR): alias of PDOUT. Writing a 1 to PDCLR[n] clears the respective
PDOUT[n] to 0. Writing a 0 has no effect. Applicable only when the pin is configured as GPIO output
(PFUNC[n] = 1 and PDIR[n] = 1).
See the register descriptions in Section 24.1 for details on the mapping of each McASP pin to the register
bits. Figure 24-21 shows the pin control block diagram.
24.0.21.6.1 McASP Pin Control-Transmit and Receive
You must correctly set the McASP GPIO registers PFUNC and PDIR, even when McASP pins are used
for their serial port (non-GPIO) function.
Serial port functions include:
• Clock pins (ACLKX, ACLKR, AHCLKX, AHCLKR, AFSX, AFSR) used as clock inputs and outputs
• Serializer data pins (AXR[n]) used to transmit or receive
• AMUTE used as a mute output signal
When using these pins in their serial port function, you must clear PFUNC[n] to 0 for each pin, as opposed
to PFUNC[n] = 1, which makes the pin a GPIO.
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