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SPRUH91D–March 2013–Revised September 2016
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Multimedia Card (MMC)/Secure Digital (SD) Card Controller
25.2.9.5 Initialize the Time-Out Registers (MMCTOR and MMCTOD)
Specify the time-out period for responses using the MMC response time-out register (MMCTOR) and the
time-out period for reading data using the MMC data read time-out register (MMCTOD).
When the MMC/SD controller sends a command to a memory card, it must often wait for a response. The
MMC/SD controller can wait indefinitely or up to 255 memory clock cycles. If you load 0 into MMCTOR,
the MMC/SD controller waits indefinitely for a response. If you load a nonzero value into MMCTOR, the
MMC/SD controller stops waiting after the specified number of memory clock cycles and then sets a
response time-out flag (TOUTRS) in the MMC status register 0 (MMCST0). If you enable the associated
interrupt request, the MMC/SD controller also sends an interrupt request to the CPU.
When the MMC/SD controller requests data from a memory card, it can wait indefinitely for that data or it
can stop waiting after a programmable number of cycles. If you load 0 into MMCTOD, the MMC/SD
controller waits indefinitely. If you load a nonzero value into MMCTOD, the MMC/SD controller waits the
specified number of memory clock cycles and then sets a read data time-out flag (TOUTRD) in MMCST0.
If you enable the associated interrupt request, the MMC/SD controller also sends an interrupt request to
the CPU.
25.2.9.6 Initialize the Data Block Registers (MMCBLEN and MMCNBLK)
Specify the number of bytes in a data block in the MMC block length register (MMCBLEN) and the number
of blocks in a multiple-block transfer in the MMC number of blocks register (MMCNBLK).
You must define the size for each block of data transferred between the MMC/SD controller and a memory
card in MMCBLEN. The valid size depends on the type of read/write operations. A length of 0 bytes is
prohibited.
For multiple-block transfers, you must specify how many blocks of data are to be transferred between the
MMC/SD controller and a memory card. You can specify an infinite number of blocks by loading 0 into
MMCNBLK. When MMCNBLK = 0, the MMC/SD controller continues to transfer data blocks until the
transferring is stopped with a STOP_TRANSMISSION command. To transfer a specific number of blocks,
load MMCNBLK with a value from 1 to 65 535.
25.2.9.7 Monitoring Activity in the MMC/SD Mode
This section describes registers and specific register bits that you can use to obtain the status of the
MMC/SD controller in the MMC/SD mode. You can determine the status of the MMC/SD controller by
reading the bits in the MMC status register 0 (MMCST0) and MMC status register 1 (MMCST1).
25.2.9.7.1 Determining Whether New Data is Available in MMCDRR
The MMC/SD controller sets the DRRDY bit in MMCST0 when the data in the FIFO is greater than the
threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled
(EDRRDY = 1 in MMCIM), the processor is notified of the event by an interrupt. A read of the MMC data
receive register (MMCDDR) clears the DRRDY flag.
25.2.9.7.2 Verifying that MMCDXR is Ready to Accept New Data
The MMC/SD controller sets the DXRDY bit in MMCST0 when the amount of data in the FIFO is less than
the threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled
(EDXRDY = 1 in MMCIM), the CPU is notified of the event by an interrupt.
25.2.9.7.3 Checking for CRC Errors
The MMC/SD controller sets the CRCRS, CRCRD, and CRCWR bits in MMCST0 in response to the
corresponding CRC errors of command response, data read, and data write. If the interrupt request is
enabled (ECRCRS/ECRCRD/ECRCWR = 1 in MMCIM), the CPU is notified of the CRC error by an
interrupt.
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