Revision History
www.ti.com
2206
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Revision History
• Figure 29-32: Corrected SCICLEARINT register bit name for bit 30. (CLR PBE INT) ...................................... 1678
• Table 29-28: Corrected bit name in Note to SET TX INT ....................................................................... 1699
• Chapter 30: Serial Communication Interface (SCI) Module................................................................. 1717
• Section 30.1.2: Changed Baud Clock Generator bullet to VCLK............................................................... 1718
• Equation 57: Updated equation. Changed VBUSPCLK to VCLK .............................................................. 1722
• Equation 58: Updated equation. Changed VBUSPCLK to VCLK .............................................................. 1722
• Section 30.5: Updated both paragraphs........................................................................................... 1729
• Section 30.5: Updated procedure in second paragraph ......................................................................... 1729
• Section 30.5.1: Updated last paragraph ........................................................................................... 1730
• Section 30.5.2: Updated last paragraph ........................................................................................... 1730
• Section 30.5.2: Changed number 2 in second paragraph to Transmit Interrupt ............................................. 1730
• Equation 59: Updated equation. Changed VBUSPLCK to VCLK .............................................................. 1751
• Equation 60: Updated equation. Changed VBUSPLCK to VCLK .............................................................. 1751
• Section 30.8.2: Changed first bullet ................................................................................................ 1763
• Table 30-33: Changed Pull Control = Enabled when device is under reset .................................................. 1764
• Chapter 31: Inter-Integrated Circuit (I2C) Module ............................................................................ 1765
• Table 31-7: Changed fourth paragraph in Description of XSMT bit............................................................ 1784
• Section 31.6.21: Changed paragraph.............................................................................................. 1798
• Section 31.6.22: Changed paragraph.............................................................................................. 1799
• Section 31.6.23: Changed paragraph.............................................................................................. 1799
• Table 31-32: Updated Description of SDAPDR and SCLPDR bits. 0 = enabled; 1 = disabled ............................ 1799
• Section 31.6.24: Changed paragraph.............................................................................................. 1800
• Section 31.6.25: Changed paragraph.............................................................................................. 1800
• Table 31-35: Changed Pull Control = Enabled when device is under reset .................................................. 1801
• Chapter 32: EMAC/MDIO Module................................................................................................. 1803
• Figure 32-7: Added figure. Subsequent figures renumbered ................................................................... 1815
• Figure 32-8: Added figure. Subsequent figures renumbered ................................................................... 1816
• Figure 32-9: Added figure. Subsequent figures renumbered ................................................................... 1817
• Figure 32-28: Changed default value of REV bit to 0007 0105h ............................................................... 1867
• Table 32-25: Changed Value column of REV bit to 0007 0105h............................................................... 1867
• Table 32-68: Changed Description of GMIIEN bit................................................................................ 1904
• Chapter 33: Enhanced Capture (eCAP) Module............................................................................... 1927
• Chapter 34: Enhanced Quadrature Encoder Pulse (eQEP) Module....................................................... 1957
• Chapter 35: Enhanced Pulse Width Modulator (ePWM) Module........................................................... 1995
• Chapter 36: Data Modification Module (DMM)................................................................................. 2108
• Figure 36-22: Updated Read/Write value of all bits to R/WP-0................................................................. 2141
• Figure 36-22: Updated LEGEND to includ e WP................................................................................. 2141
• Table 36-22: Changed Description of all bits to Privilege mode (write) ....................................................... 2141
• Figure 36-23: Updated Read/Write value of all bits to R/WP-0................................................................. 2142
• Figure 36-23: Updated LEGEND to include WP.................................................................................. 2142
• Table 36-23: Changed Description of all bits to Privilege mode (write) ....................................................... 2142
• Figure 36-24: Updated Read/Write value of all bits to R/WP-0................................................................. 2144
• Figure 36-24: Updated LEGEND to include WP.................................................................................. 2144
• Figure 36-25: Updated Read/Write value of all bits to R/WP-0................................................................. 2145
• Figure 36-25: Updated LEGEND to include WP.................................................................................. 2145
• Table 36-25: Changed Description of all bits to Privilege mode (write) ....................................................... 2145
• Figure 36-26: Updated Read/Write value of all bits to R/WP-0................................................................. 2146
• Figure 36-26: Updated LEGEND to include WP.................................................................................. 2146
• Table 36-26: Changed Description of all bits to Privilege mode (write) ....................................................... 2146
• Figure 36-27: Updated Read/Write value of all bits to R/WP-0................................................................. 2148
• Figure 36-27: Updated LEGEND to include WP.................................................................................. 2148
• Table 36-27: Changed Description of all bits to Privilege mode (write) ....................................................... 2148
• Table 36-27: Changed Description of CLKCLR and SYNCCLR bits. Corrected bits to CLKOUT and SYNCOUT...... 2148
To Next Page
Loading...
