Registers
www.ti.com
1202
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Serial Peripheral Interface (SPI)
Table 27-10. SPI Global Control Register 1 (SPIGCR1) Field Descriptions (continued)
Bit Field Value Description
1-0 CLKMOD,MASTER 0-3h These two bits (CLKMOD,MASTER) determine whether the SPI operates in master or slave
mode.
0 SLAVE MODE. SPIx_CLK is an input from the master who initiates the transfers. Data is
transmitted on the SPIx_SOMI pin and received on the SPIx_SIMO pin. The SPIx_SCS[n] pin is
an input pin if configured as SPI slave chip select. The SPIx_ENA pin is an output pin if
configured as the SPI enable pin.
1h-2h Reserved
3h MASTER MODE. SPIx_CLK is an output and the SPI initiates transfers. Data is transmitted on
the SPIx_SIMO pin and received on the SPIx_SOMI pin. The SPIx_SCS[n] pin is an output pin
if configured as SPI slave chip select. The SPIx_ENA pin is an input pin if configured as the SPI
enable pin.
To Next Page