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Architecture
1375
SPRUH91D–March 2013–Revised September 2016
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Universal Serial Bus 2.0 (USB) Controller
31.2.8.10 DMA State Registers
The port must store and maintain state information for each transmit and receive port/channel. The state
information is referred to as the Tx DMA State and Rx DMA State.
31.2.8.10.1 Transmit DMA State Registers
The Tx DMA State is a combination of control fields and protocol specific port scratchpad space used to
manipulate data structures and transmit packets. Each transmit channel has two queues. Each queue has
a one head descriptor pointer and one completion pointer. There are four Tx DMA State registers; one for
each port/channel.
The following information is stored in the Tx DMA State:
• Tx Queue Head Descriptor Pointer(s)
• Tx Completion Pointer(s)
• Protocol specific control/status (port scratchpad)
31.2.8.10.2 Receive DMA State Registers
The Rx DMA State is a combination of control fields and protocol specific port scratchpad space used to
manipulate data structures in order to receive packets. Each receive channel has only one queue. Each
channel queue has one head descriptor pointer and one completion pointer. There are four Rx DMA State
registers; one for each port/channel.
The following information is stored in the Rx DMA State:
• Rx Queue Head Descriptor Pointer
• Rx Queue Completion Pointer
• Rx Buffer Offset
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