Texas Instruments TMS320C6745 DSP - Page 1406

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1406
SPRUH91D–March 2013–Revised September 2016
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Universal Serial Bus 2.0 (USB) Controller
Table 31-30. Universal Serial Bus OTG (USB0) Registers (continued)
VBUS Slave
Address
Offset Acronym Register Description Section
CDMA Registers
1000h DMAREVID CDMA Revision Identification Register Section 31.4.66
1004h TDFDQ CDMA Teardown Free Descriptor Queue Control Register Section 31.4.67
1008h DMAEMU CDMA Emulation Control Register Section 31.4.68
1800h TXGCR[0] Transmit Channel 0 Global Configuration Register Section 31.4.69
1808h RXGCR[0] Receive Channel 0 Global Configuration Register Section 31.4.70
180Ch RXHPCRA[0] Receive Channel 0 Host Packet Configuration Register A Section 31.4.71
1810h RXHPCRB[0] Receive Channel 0 Host Packet Configuration Register B Section 31.4.72
1820h TXGCR[1] Transmit Channel 1 Global Configuration Register Section 31.4.69
1828h RXGCR[1] Receive Channel 1 Global Configuration Register Section 31.4.70
182Ch RXHPCRA[1] Receive Channel 1 Host Packet Configuration Register A Section 31.4.71
1830h RXHPCRB[1] Receive Channel 1 Host Packet Configuration Register B Section 31.4.72
1840h TXGCR[2] Transmit Channel 2 Global Configuration Register Section 31.4.69
1848h RXGCR[2] Receive Channel 2 Global Configuration Register Section 31.4.70
184Ch RXHPCRA[2] Receive Channel 2 Host Packet Configuration Register A Section 31.4.71
1850h RXHPCRB[2] Receive Channel 2 Host Packet Configuration Register B Section 31.4.72
1860h TXGCR[3] Transmit Channel 3 Global Configuration Register Section 31.4.69
1868h RXGCR[3] Receive Channel 3 Global Configuration Register Section 31.4.70
186Ch RXHPCRA[3] Receive Channel 3 Host Packet Configuration Register A Section 31.4.71
1870h RXHPCRB[3] Receive Channel 3 Host Packet Configuration Register B Section 31.4.72
2000h DMA_SCHED_CTRL CDMA Scheduler Control Register Section 31.4.73
2800h-28FCh WORD[0]-WORD[63] CDMA Scheduler Table Word 0-63 Registers Section 31.4.74
Queue Manager (QMGR) Registers
4000h QMGRREVID QMGR Revision Identification Register Section 31.4.75
4008h DIVERSION QMGR Queue Diversion Register Section 31.4.76
4020h FDBSC0 QMGR Free Descriptor/Buffer Starvation Count Register 0 Section 31.4.77
4024h FDBSC1 QMGR Free Descriptor/Buffer Starvation Count Register 1 Section 31.4.78
4028h FDBSC2 QMGR Free Descriptor/Buffer Starvation Count Register 2 Section 31.4.79
402Ch FDBSC3 QMGR Free Descriptor/Buffer Starvation Count Register 3 Section 31.4.80
4080h LRAM0BASE QMGR Linking RAM Region 0 Base Address Register Section 31.4.81
4084h LRAM0SIZE QMGR Linking RAM Region 0 Size Register Section 31.4.82
4088h LRAM1BASE QMGR Linking RAM Region 1 Base Address Register Section 31.4.83
4090h PEND0 QMGR Queue Pending Register 0 Section 31.4.84
4094h PEND1 QMGR Queue Pending Register 1 Section 31.4.85
5000h +
16 × R
QMEMRBASE[R] QMGR Memory Region R Base Address Register (R = 0 to
15)
Section 31.4.86
5004h +
16 × R
QMEMRCTRL[R] QMGR Memory Region R Control Register (R = 0 to 15) Section 31.4.87
600Ch +
16 × N
CTRLD[N] QMGR Queue N Control Register D (N = 0 to 63) Section 31.4.88
6800h +
16 × N
QSTATA[N] QMGR Queue N Status Register A (N = 0 to 63) Section 31.4.89
6804h +
16 × N
QSTATB[N] QMGR Queue N Status Register B (N = 0 to 63) Section 31.4.90
6808h +
16 × N
QSTATC[N] QMGR Queue N Status Register C (N = 0 to 63) Section 31.4.91