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19
SPRUH91D–March 2013–Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Contents
31.4.13 USB Interrupt Mask Set Register (INTMSKSETR)...................................................... 1417
31.4.14 USB Interrupt Mask Clear Register (INTMSKCLRR) ................................................... 1418
31.4.15 USB Interrupt Source Masked Register (INTMASKEDR) .............................................. 1419
31.4.16 USB End of Interrupt Register (EOIR) .................................................................... 1420
31.4.17 Generic RNDIS EP1 Size Register (GENRNDISSZ1) ................................................. 1420
31.4.18 Generic RNDIS EP2 Size Register (GENRNDISSZ2) ................................................. 1421
31.4.19 Generic RNDIS EP3 Size Register (GENRNDISSZ3) ................................................. 1421
31.4.20 Generic RNDIS EP4 Size Register (GENRNDISSZ4) ................................................. 1422
31.4.21 Function Address Register (FADDR) ..................................................................... 1422
31.4.22 Power Management Register (POWER) ................................................................. 1423
31.4.23 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................ 1424
31.4.24 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)............................................. 1425
31.4.25 Interrupt Enable Register for INTRTX (INTRTXE) ...................................................... 1426
31.4.26 Interrupt Enable Register for INTRRX (INTRRXE)...................................................... 1426
31.4.27 Interrupt Register for Common USB Interrupts (INTRUSB)............................................ 1427
31.4.28 Interrupt Enable Register for INTRUSB (INTRUSBE) .................................................. 1428
31.4.29 Frame Number Register (FRAME) ........................................................................ 1428
31.4.30 Index Register for Selecting the Endpoint Status and Control Registers (INDEX).................. 1429
31.4.31 Register to Enable the USB 2.0 Test Modes (TESTMODE)........................................... 1429
31.4.32 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)........................... 1430
31.4.33 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) .......................... 1431
31.4.34 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ............................... 1432
31.4.35 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR).......................... 1433
31.4.36 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ............................... 1434
31.4.37 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ........................... 1435
31.4.38 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) .......................... 1436
31.4.39 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ............................... 1437
31.4.40 Count 0 Register (COUNT0) ............................................................................... 1438
31.4.41 Receive Count Register (RXCOUNT)..................................................................... 1438
31.4.42 Type Register (Host mode only) (HOST_TYPE0) ...................................................... 1439
31.4.43 Transmit Type Register (Host mode only) (HOST_TXTYPE) ......................................... 1439
31.4.44 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .......................................... 1440
31.4.45 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................ 1440
31.4.46 Receive Type Register (Host mode only) (HOST_RXTYPE) ......................................... 1441
31.4.47 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................ 1442
31.4.48 Configuration Data Register (CONFIGDATA) ........................................................... 1443
31.4.49 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ......................................... 1444
31.4.50 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ......................................... 1444
31.4.51 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ......................................... 1445
31.4.52 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ......................................... 1445
31.4.53 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ......................................... 1446
31.4.54 Device Control Register (DEVCTL) ....................................................................... 1446
31.4.55 Transmit Endpoint FIFO Size (TXFIFOSZ)............................................................... 1447
31.4.56 Receive Endpoint FIFO Size (RXFIFOSZ) ............................................................... 1447
31.4.57 Transmit Endpoint FIFO Address (TXFIFOADDR)...................................................... 1448
31.4.58 Receive Endpoint FIFO Address (RXFIFOADDR) ...................................................... 1448
31.4.59 Hardware Version Register (HWVERS) .................................................................. 1449
31.4.60 Transmit Function Address (TXFUNCADDR)............................................................ 1450
31.4.61 Transmit Hub Address (TXHUBADDR)................................................................... 1450
31.4.62 Transmit Hub Port (TXHUBPORT)........................................................................ 1450
31.4.63 Receive Function Address (RXFUNCADDR) ............................................................ 1451
31.4.64 Receive Hub Address (RXHUBADDR) ................................................................... 1451
31.4.65 Receive Hub Port (RXHUBPORT) ........................................................................ 1451
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