SYSCFG Registers
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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
Table 10-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued)
Bit Field
ZKB
Ball
(1)
PTP
Pin
(2)
Value Description
15-12 PINMUX0_15_12 C14 86 EMB_CLK Control
0 Pin is 3-stated.
1h Selects Function EMB_CLK from EMIFB LPSC (CLK1)
2h Selects Function EMB_CLK from PLL DIV4P5 or SYSCLK5 (CLK2)
3h-Fh Reserved
11-8 PINMUX0_11_8 C13 88 EMB_SDCKE Control
0 Pin is 3-stated.
1h Selects Function EMB_SDCKE
2h-Fh Reserved
7-4 PINMUX0_7_4 J5 — GP7[15]/EMU[0] Control
0 Pin is 3-stated.
1h Selects Function GP7[15]
2h-7h Reserved
8h Selects Function EMU[0]
9h-Fh Reserved
3-0 PINMUX0_3_0 K1 157 GP7[14] Control. GP7[14] is initially configured as a reserved function after
reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. You should carefully
consider the system implications of this pin being in an unknown state after
reset.
0 Reserved
1h Selects Function GP7[14]
2h-Fh Reserved