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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
19.2.6.7 Self-Refresh Mode
The EMIFB can be programmed to enter the self-refresh state by setting the LP_MODE bit and SR_PD bit
of the SDRAM refresh control register (SDRFC) to 1 and 0, respectively. This will cause the EMIFB to
issue the SLFR command after completing any outstanding SDRAM access requests and clearing the
refresh backlog counter by performing one or more auto refresh cycles. This places the attached SDRAM
device into self-refresh mode in which it consumes a minimal amount of power while performing its own
refresh cycles.
While in the self-refresh state, the EMIFB continues to service register accesses as normal.
The EMIFB will exit from the self-refresh state, if any of the following events occur:
• The LP_MODE bit of SDRFC is cleared to 0
• The SR_PD bit is set to 1
• An SDRAM accesses is requested
The EMIFB exits from the self-refresh state by driving EMB_SDCKE high and performing an auto refresh
cycle.
The attached SDRAM device must be placed into self-refresh mode when changing the frequency of
EMB_CLK using the PLL Controller. If the frequency of EMB_CLK changes while the SDRAM is not in
self-refresh mode, the memory must be reinitialized.
During Self- refresh, if memory/register access request is made, EMIFB comes out of self-refresh state
(driving EMB_SDCKE high) and executes the requests; after which it again goes back to self-refresh state
(driving EMB_SDCKE low).
To use Partial Array Self Refresh for mobile SDR, PASR bits in the SDRAM configuration 2 register must
be appropriately programmed. The EMIFB performs bank interleaving. Since the SDRAM is partially
refreshed during Partial Array Self Refresh, it is the responsibility of software to move critical data into the
banks that are going to be refreshed during Partial Array Self Refresh.
Power-Down Mode
To support low-power modes, the EMIFB can be requested to issue a POWERDOWN command to the
SDRAM by setting both the LP_MODE and SR_PD bits in the SDRAM refresh control register (SDRFC) to
1. When this bit is set, the EMIFB will continue normal operation until all outstanding memory access
requests have been serviced and the SDRAM refresh backlog (if there is one) has been cleared. At this
point the EMIFB will enter the power-down state. Upon entering this state the EMIF will issue a
POWERDOWN command (same as a NOP command but driving EMB_SDCKE low on the same cycle).
The EMIFB then maintains EMB_SDCKE low until it exits the power-down state.
During the power-down state, the EMIFB services synchronous memory and register accesses as normal.
The EMIFB will exit from the power-down state, if any of the following events occur:
• The LP_MODE bit of SDRFC is cleared to 0
• The SR_PD bit is cleared to 0
• An SDRAM accesses is requested
• Refresh (REFR) command is to be sent to SDRAM.
During power-down, if memory/register access request is made, EMIFB comes out of the power-down
state (driving EMB_SDCKE high) and executes the requests; after which it again goes back to the power-
down state (driving EMB_SDCKE low).
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