Architecture
www.ti.com
794
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface B (EMIFB)
Partial Array Self Refresh for mobile SDRAM
This is applicable only to mobile SDRAM, when using the addressing scheme as described in Table 19-
16. For additional power savings during self-refresh, the partial array self-refresh (PASR) feature of mobile
SDR allows to select the amount of memory that will be refreshed during self-refresh. Use the partial array
self-refresh (PASR) bit field in the SDRAM configuration 2 register (SDCFG2) to select the amount of
memory to refresh during self-refresh. As shown in PASR Bitfield in SDRAM Configuration 2 Register
(SDCFG2) Configuration you may select either 4, 2, 1, 1/2, or 1/4 bank(s). The PASR bits are loaded into
the extended mode register of the mobile SDR device, during autoinitialization (see Section 19.2.6.4). The
EMIFB performs bank interleaving when the internal bank position (IBANKPOS) bit in SDRAM
configuration register (SDCFG) is cleared to 0. Since the SDRAM banks are only partially refreshed during
partial array self-refresh, it is recommended that you set IBANKPOS to 1 to avoid bank interleaving. Refer
to Section 19.2.6.10 for more information on IBANKPOS and addressing mapping in general.
PASR Bitfield in SDRAM Configuration 2 Register (SDCFG2) Configuration
Bit Field Bit Value Bit Description
PASR 0 Refresh banks 0, 1, 2, and 3
1h Refresh banks 0 and 1
2h Refresh bank 0
3h Reserved
4h Reserved
5h Refresh 1/2 of bank 0
6h Refresh 1/4 of bank 0
7h Reserved
To Next Page