Registers
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SPRUH91D–March 2013–Revised September 2016
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Liquid Crystal Display Controller (LCDC)
23.3.9.2 Horizontal Synchronization Pulse Width (HSW)
NOTE: The pixel clock does not transition during the line clock pulse in passive display mode, but it
transitions in active display mode.
The 6-bit horizontal synchronization pulse width (HSW) field is used to specify the pulse width of the line
clock in passive mode, or horizontal synchronization pulse in active mode. The line clock (or
LCD_HSYNC) is asserted each time a line or row of pixels is output to the display and a programmable
number of pixel clock delays have elapsed. When line clock is asserted, the value in HSW is transferred to
a 6-bit down counter that uses the programmed pixel clock frequency to decrement. When the counter
reaches zero, the line clock is negated. HSW can be programmed to generate a line clock pulse width
ranging from 1–64 pixel clock periods (program to value required minus 1).
23.3.9.3 Horizontal Front Porch (HFP)
NOTE: The pixel clock does not transition during these dummy pixel clock cycles in passive display
mode, but it transitions continuously in active display mode.
The 8-bit horizontal front porch (HFP) field is used to specify the number of dummy pixel clocks to insert at
the end of each line or row of pixels before pulsing the line clock(or LCD_HSYNC) pin. Once a complete
line of pixels is transmitted to the LCD driver, the value in HFP is used to count the number of pixel clocks
to wait before pulsing the line clock. HFP generates a wait period ranging from 1–256 pixel clock cycles
(program to value required minus 1).
23.3.9.4 Horizontal Back Porch (HBP)
NOTE: The pixel clock does not transition during these dummy pixel clock cycles in passive display
mode, but it transitions continuously in active display mode.
The 8-bit horizontal back porch (HBP) field is used to specify the number of dummy pixel clocks to insert
at the beginning of each line or row of pixels. After the line clock(or LCD_HSYNC) for the previous line
has been negated, the value in HBP is used to count the number of pixel clocks to wait before starting to
output the first set of pixels in the next line. HBP generates a wait period ranging from 1–256 pixel clock
cycles (program to value required minus 1).
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