Texas Instruments TMS570LC4357 - Page 2204

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2204
SPNU563A–March 2018
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Revision History
• Section 26.3.1.22: Updated register bit names to reflect corresponding message buffer number......................... 1311
• Section 26.3.1.23: Updated register bit names to reflect corresponding message buffer number......................... 1315
• Section 26.3.1.24: Updated register bit names to reflect corresponding message buffer number......................... 1319
• Section 26.3.2.2.5: Updated paragraph............................................................................................ 1350
• Section 26.3.2.2.6: Updated paragraph............................................................................................ 1352
• Chapter 27: Controller Area Network (DCAN) Module....................................................................... 1417
• Equation 38: Updated equation..................................................................................................... 1424
• Equation 39: Updated equation..................................................................................................... 1424
• Section 27.3.2.4: Changed t
q
= 1 µs ............................................................................................... 1425
• Equation 40: Updated equation..................................................................................................... 1425
• Equation 41: Updated equation..................................................................................................... 1425
• Section 27.16: Changed subsection ............................................................................................... 1454
• Table 27-6: Added Core Release Register........................................................................................ 1454
• Figure 27-21: Updated Read/Write value of PER bit to R/C-0.................................................................. 1459
• Table 27-9: Updated Value column of REC bit to 0-7Fh ........................................................................ 1461
• Table 27-9: Updated Description of REC bit (Values from 0 to 127) .......................................................... 1461
• Table 27-11: Corrected Value column range of Int1ID and Int0ID bits to 1h-40h............................................ 1463
• Table 27-13: Corrected Value column range of Message Number bit to 1h-FFh ............................................ 1465
• Table 27-13: Updated Description of Message Number bit. Only values 1h-40h are valid. Values 41h-FFh are
invalid................................................................................................................................... 1465
• Section 27.17.8: Added subsection. Subsequent subsections, figures, and tables renumbered .......................... 1465
• Figure 27-29: Changed Read/Write value of DEFLG_DIAG and SEFLG_DIAG bits to R/W1C-0......................... 1466
• Figure 27-30: Changed Read/Write value of DEFLG and SEFLG bits to R/W1C-0 ......................................... 1467
• Table 27-18: Corrected Value column range of Message Number bit to 1h-FFh ............................................ 1468
• Table 27-18: Updated Description of Message Number bit. Only values 1h-40h are valid. Values 41h-FFh are
invalid................................................................................................................................... 1468
• Figure 27-32: Corrected register bit name to ABO_TIME ....................................................................... 1469
• Table 27-19: Corrected register bit name to ABO_TIME........................................................................ 1469
• Table 27-25: Corrected Value column range of Message Number bit to 1h-40h ............................................ 1479
• Table 27-28: Updated Description of EoB bit ..................................................................................... 1485
• Section 27.17.28: Changed sixth paragraph ...................................................................................... 1487
• Table 27-35: Changed the Func Bit description for Value = 1. (as an input to receive CAN data) ........................ 1495
• Chapter 28: Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP).... 1497
• Chapter 28: Global: Updated all VBUSPCLK signals to VCLK................................................................. 1497
• Chapter 28: Global: Changed SPISCS to SPICS ................................................................................ 1497
• Table 28-1: Changed SPIENA enabled description in Slave Mode............................................................ 1499
• Section 28.2.1: Changed first sentence in second paragraph .................................................................. 1500
• Figure 28-10: Corrected figure title................................................................................................. 1511
• Figure 28-10: Corrected bits D11-D8 to 1110..................................................................................... 1511
• Figure 28-11: Corrected figure title................................................................................................. 1511
• Section 28.2.6.3: Updated first two paragraphs .................................................................................. 1515
• Section 28.2.9.1: Changed sixth sentence. Added T2EDELAY ................................................................ 1529
• Section 28.2.9.2: Changed second sentence. Added C2EDELAY............................................................. 1530
• Section 28.2.11.1: Changed second sentence ................................................................................... 1533
• Section 28.2.11.2: Changed second sentence ................................................................................... 1534
• Table 28-8: Added SPIPC9 at address offset 68h ............................................................................... 1535
• Table 28-10: Changed Description of CLKMOD bit for Value = 1. (SPIENA is an input.) .................................. 1537
• Table 28-15: Corrected Description of SIMODIR0 bit............................................................................ 1545
• Table 28-21: Updated Description of all bits to clarify that bit is a pull control disable ...................................... 1554
• Table 28-23: Changed Description of TXDATA bit. Added last Note.......................................................... 1556
• Section 28.3.16: Added NOTE...................................................................................................... 1557
• Table 28-24: Updated Description of CSNR and TXDATA bits ................................................................ 1557
• Table 28-25: Added table. Subsequent tables renumbered .................................................................... 1559
• Table 28-26: Corrected Description of RXEMPTY bit. (SPIBUF to RXDATA)................................................ 1560