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Registers
953
SPRUH91D–March 2013–Revised September 2016
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Liquid Crystal Display Controller (LCDC)
23.3.3.1 Frame Done (DONE)
When the LCD is disabled by clearing the LCD Raster Control enable bit (RASTER_EN = 0) in the LCD
Raster Control Register, the LCD allows the current frame to complete before it is disabled. After the last
set of pixels is clocked out onto the LCD data pins by the pixel clock, the LCD is disabled and DONE is
set.
• DONE = 1 when the frame is complete.
• DONE = 0 as long as the frame is not complete.
The frame done (DONE) bit signals the frame is complete. It is cleared when the RASTER_EN bit is set to
1 (turned ON).
23.3.3.2 Frame Synchronization Lost (SYNC)
The frame synchronization lost (SYNC) bit is set if the LCD controller detects a frame synchronization
error. A frame synchronization error can occur for one of two reasons:
• when the LCD controller attempts to read what it believes to be the first word of the video buffer but
cannot be recognized as such
• if the LCD controller is starved of data, which can happen due to insufficient bandwidth from the source
of LCD data through the system interconnect to the LCD controller
To alleviate data bandwidth bottleneck issues to the LCD controller, the following configuration settings
can be experimented with:
• Increase EMIFB (if used) Command Re-Ordering (BPRIO) setting from default to a value such as 10h
to 20h
• Increase priority for LCD controller DMA
• Increase burst size setting for LCD controller DMA
• Run the EMIFB (if used) at maximum clock speed
This bit is cleared by disabling the LCD controller (RASTER_EN = 0). This also resets the input FIFO in
the DMA controller.
• SYNC = 1 when a frame synchronization lost occurred.
• SYNC = 0 as long as no frame synchronization error occurs.
23.3.3.3 AC-Bias Count Status (ABC)
The ac-bias count status (ABC) bit is set each time the ac-bias line transitions a particular number of times
as specified by the ac-bias line transitions per interrupt (ACB_I) field in LCD Raster Timing Register 2. If
ACB_I is programmed with a non-zero value, a counter is loaded with the value in ACB_I and is
decremented each time the ac-bias line reverses state. When the counter reaches zero, the ABC bit is set
that signals an interrupt request to the interrupt controller. The counter reloads using the value in ACB_I,
but does not start to decrement again until you clear ABC by writing 0 to the LCD status register.
• ABC = 1 when the ac-bias transition counter ACB_I has decremented to 0
• ABC = 0 as long as ACB_I has not decremented to 0
23.3.3.4 FIFO Underflow Status (FUF)
The FIFO underflow status (FUF) bit is set when the input FIFO is completely empty and the LCD data
pins driver logic attempts to fetch data from the FIFO. This bit is cleared by disabling the LCD controller
(RASTER_EN = 0). To recover from this condition and restart normal function of the LCDC, the peripheral
needs to be reset through the Power and Sleep Controller (PSC).
• FUF = 1 when the dithering logic is not supplying data to the FIFO at a sufficient rate.
• FUF = 0 as long as FIFO has not underrun.
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