Texas Instruments TMS570LC4357 - Page 84

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84
SPNU563A–March 2018
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List of Tables
20-89. DMA Memory Protection Region 7 Start Address Register (DMAMPR7S) Field Descriptions................. 781
20-90. DMA Memory Protection Region 7 End Address Register (DMAMPR7E) Field Descriptions.................. 781
20-91. DMA Single-Bit ECC Control Register (DMASECCCTRL) Field Description ..................................... 782
20-92. DMA ECC Single-Bit Error Address Register (DMAECCSBE) Field Descriptions ............................... 783
20-93. FIFO A Status Register (FIFOASTAT) Field Descriptions .......................................................... 784
20-94. FIFO B Status Register (FIFOBSTAT) Field Descriptions .......................................................... 784
20-95. DMA Request Polarity Select Register (DMAREQPS1) Field Descriptions....................................... 785
20-96. DMA Request Polarity Select Register (DMAREQPS1) Field Descriptions....................................... 785
20-97. Transaction Parity Error Event Control Register (TERECTRL) Field Descriptions .............................. 786
20-98. TER Event Flag Register (TERFLAG) Field Descriptions........................................................... 786
20-99. TER Event Channel Offset Register (TERROFFSET) Field Descriptions......................................... 787
20-100. Initial Source Address Register (ISADDR) Field Descriptions..................................................... 788
20-101. Initial Destination Address Register (IDADDR) Field Descriptions ............................................... 788
20-102. Initial Transfer Count Register (ITCOUNT) Field Descriptions .................................................... 789
20-103. Channel Control Register (CHCTRL) Field Descriptions........................................................... 790
20-104. Element Index Offset Register (EIOFF) Field Descriptions ....................................................... 791
20-105. Frame Index Offset Register (FIOFF) Field Descriptions .......................................................... 791
20-106. Current Source Address Register (CSADDR) Field Descriptions ................................................ 792
20-107. Current Destination Address Register (CDADDR) Field Descriptions............................................ 792
20-108. Current Transfer Count Register (CTCOUNT) Field Descriptions ................................................ 792
21-1. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories ......................................... 796
21-2. EMIF Pins Specific to SDRAM.......................................................................................... 797
21-3. EMIF Pins Specific to Asynchronous Memory ........................................................................ 797
21-4. EMIF SDRAM Commands............................................................................................... 798
21-5. Truth Table for SDRAM Commands ................................................................................... 798
21-6. 16-bit EMIF Address Pin Connections ................................................................................. 800
21-7. Description of the SDRAM Configuration Register (SDCR)......................................................... 801
21-8. Description of the SDRAM Refresh Control Register (SDRCR).................................................... 801
21-9. Description of the SDRAM Timing Register (SDTIMR).............................................................. 802
21-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ...................................... 802
21-11. SDRAM LOAD MODE REGISTER Command........................................................................ 803
21-12. Refresh Urgency Levels ................................................................................................. 804
21-13. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM ................................................... 809
21-14. Normal Mode vs. Select Strobe Mode ................................................................................. 810
21-15. Description of the Asynchronous m Configuration Register (CEnCFG)........................................... 812
21-16. Description of the Asynchronous Wait Cycle Configuration Register (AWCC) .................................. 813
21-17. Description of the EMIF Interrupt Mask Set Register (INTMSKSET) .............................................. 813
21-18. Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR) ............................................ 813
21-19. Asynchronous Read Operation in Normal Mode ..................................................................... 814
21-20. Asynchronous Write Operation in Normal Mode ..................................................................... 816
21-21. Asynchronous Read Operation in Select Strobe Mode.............................................................. 818
21-22. Asynchronous Write Operation in Select Strobe Mode.............................................................. 820
21-23. Interrupt Monitor and Control Bit Fields................................................................................ 824
21-24. External Memory Interface (EMIF) Registers ......................................................................... 828
21-25. Module ID Register (MIDR) Field Descriptions ....................................................................... 828
21-26. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions................................. 829
21-27. SDRAM Configuration Register (SDCR) Field Descriptions ........................................................ 830
21-28. SDRAM Refresh Control Register (SDRCR) Field Descriptions ................................................... 831
21-29. Asynchronous n Configuration Register (CEnCFG) Field Descriptions ........................................... 832