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SPNU563A–March 2018
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List of Tables
20-40. LFS Interrupt Enable Reset Register (LFSINTENAR) Field Descriptions......................................... 746
20-41. HBC Interrupt Enable Set Register (HBCINTENAS) Field Descriptions .......................................... 747
20-42. HBC Interrupt Enable Reset Register (HBCINTENAR) Field Descriptions ....................................... 747
20-43. BTC Interrupt Enable Reset Register (BTCINTENAS) Field Descriptions ........................................ 748
20-44. BTC Interrupt Enable Reset Register (BTCINTENAR) Field Descriptions ........................................ 748
20-45. Global Interrupt Flag Register (GINTFLAG) Field Descriptions .................................................... 749
20-46. FTC Interrupt Flag Register (FTCFLAG) Field Descriptions ........................................................ 749
20-47. LFS Interrupt Flag Register (LFSFLAG) Field Descriptions......................................................... 750
20-48. HBC Interrupt Flag Register (HBCFLAG) Field Descriptions ....................................................... 750
20-49. BTC Interrupt Flag Register (BTCFLAG) Field Descriptions........................................................ 751
20-50. FTCA Interrupt Channel Offset Register (FTCAOFFSET) Field Descriptions .................................... 752
20-51. LFSA Interrupt Channel Offset Register (LFSAOFFSET) Field Descriptions..................................... 753
20-52. HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions ................................... 754
20-53. BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions.................................... 755
20-54. FTCB Interrupt Channel Offset Register (FTCBOFFSET) Field Descriptions .................................... 756
20-55. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions..................................... 757
20-56. HBCB Interrupt Channel Offset Register (HBCBOFFSET) Field Descriptions ................................... 758
20-57. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions.................................... 759
20-58. Port Control Register (PTCRL) Field Descriptions ................................................................... 760
20-59. RAM Test Control Register (RTCTRL) Field Descriptions .......................................................... 761
20-60. Debug Control Register (DCTRL) Field Descriptions ................................................................ 762
20-61. Watch Point Register (WPR) Field Descriptions...................................................................... 763
20-62. Watch Mask Register (WMR) Field Descriptions..................................................................... 763
20-63. FIFO A Active Channel Source Address Register (FAACSADDR) Field Descriptions .......................... 764
20-64. FIFO A Active Channel Destination Address Register (FAACDADDR) Field Descriptions..................... 764
20-65. Port B Active Channel Transfer Count Register (FAACTC) Field Descriptions .................................. 764
20-66. FIFO B Active Channel Source Address Register (FBACSADDR) Field Descriptions .......................... 765
20-67. FIFO B Active Channel Destination Address Register (FBACDADDR) Field Descriptions..................... 765
20-68. FIFO B Active Channel Transfer Count Register (FBACTC) Field Descriptions ................................. 765
20-69. ECC Control Register (DMAPECR) Field Descriptions.............................................................. 766
20-70. DMA ECC Error Address Register (DMAPAR) Field Descriptions ................................................. 767
20-71. DMA Memory Protection Control Register 1 (DMAMPCTRL1) Field Descriptions............................... 768
20-72. DMA Memory Protection Status Register 1 (DMAMPST1) Field Descriptions ................................... 770
20-73. DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) Field Descriptions................. 771
20-74. DMA Memory Protection Region 0 End Address Register (DMAMPR0E) Field Descriptions.................. 771
20-75. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) Field Descriptions................. 772
20-76. DMA Memory Protection Region 1 End Address Register (DMAMPR1E) Field Descriptions.................. 772
20-77. DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) Field Descriptions................. 773
20-78. DMA Memory Protection Region 2 End Address Register (DMAMPR2E) Field Descriptions.................. 773
20-79. DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) Field Descriptions................. 774
20-80. DMA Memory Protection Region 3 End Address Register (DMAMPR3E) Field Descriptions.................. 774
20-81. DMA Memory Protection Control Register 2 (DMAMPCTRL2) Field Descriptions............................... 775
20-82. DMA Memory Protection Status Register 2 (DMAMPST2) Field Descriptions ................................... 777
20-83. DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) Field Descriptions................. 778
20-84. DMA Memory Protection Region 4 End Address Register (DMAMPR4E) Field Descriptions.................. 778
20-85. DMA Memory Protection Region 5 Start Address Register (DMAMPR5S) Field Descriptions................. 779
20-86. DMA Memory Protection Region 5 End Address Register (DMAMPR5E) Field Descriptions.................. 779
20-87. DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) Field Descriptions................. 780
20-88. DMA Memory Protection Region 6 End Address Register (DMAMPR6E) Field Descriptions.................. 780
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