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SPNU563A–March 2018
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List of Tables
19-15. Pending Interrupt Read Location Registers (INTREQ) Field Descriptions ........................................ 687
19-16. Interrupt Enable Set Registers (REQENASET) Field Descriptions ................................................ 688
19-17. Interrupt Enable Clear Registers (REQENACLR) Field Descriptions ............................................. 689
19-18. Wake-Up Enable Set Registers (WAKEENASET) Field Descriptions ............................................. 690
19-19. Wake-Up Enable Clear Registers (WAKEENACLR) Field Descriptions........................................... 691
19-20. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions .................................................. 692
19-21. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions................................................... 692
19-22. Capture Event Register (CAPEVT) Field Descriptions .............................................................. 693
19-23. Interrupt Control Registers Organization .............................................................................. 694
19-24. Interrupt Control Registers (CHANCTRL[0:31]) Field Descriptions ................................................ 694
20-1. DMA Ports to System Resources Mapping ........................................................................... 699
20-2. Arbitration According to Priority Queues and Priority Schemes .................................................... 706
20-3. DMA Request Line Connection ......................................................................................... 710
20-4. Maximum Number of DMA Transactions per Channel in Non-Bypass Mode..................................... 715
20-5. Maximum Number of DMA Transactions per Channel in Bypass Mode .......................................... 715
20-6. ECC Mapping ............................................................................................................. 719
20-7. DMA Control Registers................................................................................................... 721
20-8. Control Packet Memory Map............................................................................................ 723
20-9. Global Control Register (GCTRL) Field Descriptions ................................................................ 724
20-10. Channel Pending Register (PEND) Field Descriptions .............................................................. 725
20-11. DMA Status Register (DMASTAT) Field Descriptions ............................................................... 725
20-12. DMA Revision ID Register Description ................................................................................ 726
20-13. HW Channel Enable Set and Status Register (HWCHENAS) Field Descriptions................................ 727
20-14. HW Channel Enable Reset and Status Register (HWCHENAR) Field Descriptions ............................ 727
20-15. SW Channel Enable Set and Status Register (SWCHENAS) Field Descriptions................................ 728
20-16. SW Channel Enable Reset and Status Register (SWCHENAR) Field Descriptions............................. 728
20-17. Channel Priority Set Register (CHPRIOS) Field Descriptions ...................................................... 729
20-18. Channel Priority Reset Register (CHPRIOR) Field Descriptions ................................................... 729
20-19. Global Channel Interrupt Enable Set Register (GCHIENAS) Field Descriptions................................. 730
20-20. Global Channel Interrupt Enable Reset Register (GCHIENAR) Field Descriptions.............................. 730
20-21. DMA Request Assignment Register 0 (DREQASI0) Field Descriptions........................................... 731
20-22. DMA Request Assignment Register 1 (DREQASI1) Field Descriptions........................................... 732
20-23. DMA Request Assignment Register 2 (DREQASI2) Field Descriptions........................................... 733
20-24. DMA Request Assignment Register 3 (DREQASI3) Field Descriptions........................................... 734
20-25. DMA Request Assignment Register 4 (DREQASI4) Field Descriptions........................................... 735
20-26. DMA Request Assignment Register 5 (DREQASI5) Field Descriptions........................................... 736
20-27. DMA Request Assignment Register 6 (DREQASI6) Field Descriptions........................................... 737
20-28. DMA Request Assignment Register 7 (DREQASI7) Field Descriptions........................................... 738
20-29. Port Assignment Register 0 (PAR0) Field Descriptions ............................................................. 739
20-30. Port Assignment Register 1 (PAR1) Field Descriptions ............................................................. 740
20-31. Port Assignment Register 2 (PAR2) Field Descriptions ............................................................. 741
20-32. Port Assignment Register 3 (PAR3) Field Descriptions ............................................................. 742
20-33. FTC Interrupt Mapping Register (FTCMAP) Field Descriptions .................................................... 743
20-34. LFS Interrupt Mapping Register (LFSMAP) Field Descriptions..................................................... 743
20-35. HBC Interrupt Mapping Register (HBCMAP) Field Descriptions ................................................... 743
20-36. BTC Interrupt Mapping Register (BTCMAP) Field Descriptions.................................................... 744
20-37. FTC Interrupt Enable Set Register (FTCINTENAS) Field Descriptions ........................................... 745
20-38. FTC Interrupt Enable Reset (FTCINTENAR) Field Descriptions ................................................... 745
20-39. LFS Interrupt Enable Set Register (LFSINTENAS) Field Descriptions ............................................ 746
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