Texas Instruments TMS570LC4357

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102
SPNU563A–March 2018
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List of Tables
35-54. Digital Compare B Control Register (DCBCTL) Field Descriptions............................................... 2104
35-55. Digital Compare Filter Offset Register (DCFOFFSET) Field Descriptions....................................... 2105
35-56. Digital Compare Capture Control Register (DCCAPCTL) Field Descriptions ................................... 2105
35-57. Digital Compare Filter Window Register (DCFWINDOW) Field Descriptions ................................... 2106
35-58. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) Field Descriptions....................... 2106
35-59. Digital Compare Counter Capture Register (DCCAP) Field Descriptions ....................................... 2107
35-60. Digital Compare Filter Window Counter Register (DCFWINDOWCNT) Field Descriptions ................... 2107
36-1. Encoding of Destination Bits in Trace Mode Packet Format ...................................................... 2111
36-2. Encoding of Status Bits in Trace Mode Packet Format ............................................................ 2111
36-3. Encoding of Write Size in Packet Format ............................................................................ 2111
36-4. Number of Clock Cycles per Packet.................................................................................. 2112
36-5. Pins Used for Data Communication .................................................................................. 2112
36-6. DMM Registers .......................................................................................................... 2115
36-7. DMM Global Control Register (DMMGLBCTRL) Field Descriptions.............................................. 2116
36-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions................................................... 2118
36-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions ................................................ 2122
36-10. DMM Interrupt Level Register (DMMINTLVL) Field Descriptions................................................. 2127
36-11. DMM Interrupt Flag Register (DMMINTFLG) Field Descriptions.................................................. 2129
36-12. DMM Interrupt Offset 1 Register (DMMOFF1) Field Descriptions ................................................ 2133
36-13. DMM Interrupt Offset 2 Register (DMMOFF1) Field Descriptions ................................................ 2134
36-14. DMM Direct Data Mode Destination Register (DMMDDMDEST) Field Descriptions........................... 2135
36-15. DMM Direct Data Mode Blocksize Register (DMMDDMBL) Field Descriptions................................. 2135
36-16. DMM Direct Data Mode Pointer Register (DMMDDMPT) Field Descriptions ................................... 2136
36-17. DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) Field Descriptions .......................... 2136
36-18. DMM Destination x Region 1 (DMMDESTxREG1) Field Descriptions ........................................... 2137
36-19. DMM Destination x Blocksize 1 (DMMDESTxBL1) Field Descriptions........................................... 2138
36-20. DMM Destination x Region 2 (DMMDESTxREG2) Field Descriptions ........................................... 2139
36-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) Field Descriptions........................................... 2140
36-22. DMM Pin Control 0 (DMMPC0) Field Descriptions ................................................................. 2141
36-23. DMM Pin Control 1 (DMMPC1) Field Descriptions ................................................................. 2142
36-24. DMM Pin Control 2 (DMMPC2) Field Descriptions ................................................................. 2144
36-25. DMM Pin Control 3 (DMMPC3) Field Descriptions ................................................................. 2145
36-26. DMM Pin Control 4 (DMMPC4) Field Descriptions ................................................................. 2146
36-27. DMM Pin Control 5 (DMMPC5) Field Descriptions ................................................................. 2148
36-28. DMM Pin Control 6 (DMMPC6) Field Descriptions ................................................................. 2149
36-29. DMM Pin Control 7 (DMMPC7) Field Descriptions ................................................................. 2151
36-30. DMM Pin Control 8 (DMMPC8) Field Descriptions ................................................................. 2152
37-1. Encoding of RAM Bits in Trace Mode Packet Format.............................................................. 2158
37-2. Encoding of Status Bits in Trace Mode Packet Format ............................................................ 2158
37-3. Encoding of SIZE bits in Trace Mode Packet Format .............................................................. 2158
37-4. Encoding of REG in Trace Mode Packet Format ................................................................... 2158
37-5. Number of Transfers/Packet........................................................................................... 2158
37-6. RTP Signals.............................................................................................................. 2161
37-7. RTP Control Registers.................................................................................................. 2163
37-8. RTP Global Control Register (RTPGLBCTRL) Field Descriptions................................................ 2164
37-9. FIFO Corresponding Addresses....................................................................................... 2166
37-10. Pins Used for Data Communication .................................................................................. 2166
37-11. RTP Trace Enable Register (RTPTRENA) Field Descriptions .................................................... 2167
37-12. RTP Global Status Register (RTPGSR) Field Descriptions ....................................................... 2169