Revision History
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SPNU563A–March 2018
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Revision History
Revision History
Changes from May 20, 2014 to February 28, 2018 .......................................................................................................... Page
• Chapter 1: Introduction.............................................................................................................. 106
• Chapter 2: Architecture.............................................................................................................. 112
• Table 2-1: Rearranged sequence of terms ......................................................................................... 115
• Figure 2-3: Updated figure. Changed R5F-1 Cache to RESERVED ............................................................ 121
• Table 2-6: Changed table. Corrected values in Valid RAM Groups and Valid RINFOL/RINFOU Register Value
columns.................................................................................................................................. 136
• Table 2-10: Changed VCLKA4_S to VCLKA4...................................................................................... 143
• Table 2-10: Changed RTICLK to RTICLK1......................................................................................... 143
• Table 2-10: Changed Special Considerations description of VCLKA1, VCLKA2, and VCLKA4. Deleted Frequency can be
as fast as HCLK frequency ........................................................................................................... 143
• Table 2-10: Changed Special Considerations description of VCLKA4_DIVR. Changed VCLKA4_S to VCLKA4......... 143
• Table 2-12: Updated signal names .................................................................................................. 147
• Table 2-31: Changed Description of bits for Value = 0 (Read) to enabled ..................................................... 160
• Section 2.5.1.13: Added second paragraph to NOTE............................................................................. 161
• Table 2-35: Changed Description of GHVSRC bit. Removed "on wakeup" .................................................... 167
• Table 2-41: Updated MSTGENA and MINITGENA values to Ah for MSIENA = 1 ............................................ 173
• Table 2-44: Corrected Description of PLLMUL bit. Value = 0h is ×1, Value = 100h is ×2 ................................... 176
• Figure 2-35: Corrected register bit fields............................................................................................ 179
• Table 2-47: Changed table to reflect updated register bit fields ................................................................. 179
• Figure 2-36: Corrected register bit fields............................................................................................ 179
• Table 2-48: Changed table to reflect updated register bit fields ................................................................. 179
• Table 2-49: Changed Description of OSCFRQCONFIGCNT bit. Writes have no effect...................................... 180
• Figure 2-38: Changed Reserved bits to 7-5 and SEL_ECP_PIN bits to 4-0 ................................................... 183
• Table 2-50: Changed Reserved bits to 7-5 and SEL_ECP_PIN bits to 4-0 .................................................... 183
• Table 2-50: Changed Description of SEL_GIO_PIN and SEL_ECP_PIN bits ................................................. 183
• Table 2-53: Changed Description of PLL1_FBSLIP_FILTER_ COUNT and PLL1_FBSLIP_FILTER_ KEY bits.......... 187
• Section 2.5.1.41: Changed paragraph............................................................................................... 194
• Section 2.5.1.41: Added NOTE....................................................................................................... 194
• Section 2.5.1.42: Changed NOTE ................................................................................................... 195
• Table 2-61: Added Note to VCLK2R and VCLKR bits ............................................................................ 195
• Section 2.5.1.45: Added NOTE....................................................................................................... 197
• Figure 2-53: Changed bit 12 to Reserved........................................................................................... 198
• Figure 2-53: Changed Reserved bits to 2-0 ........................................................................................ 198
• Figure 2-53: Deleted MPMODE bit .................................................................................................. 198
• Table 2-65: Changed Description of WDRST bit................................................................................... 198
• Table 2-65: Changed bit 12 to Reserved ........................................................................................... 198
• Table 2-65: Changed Reserved bits to 2-0 ......................................................................................... 198
• Table 2-65: Deleted MPMODE bit ................................................................................................... 198
• Figure 2-63: Changed bits 10-8 and 4-0 to Reserved............................................................................. 210
• Table 2-76: Changed bits 10-8 and 4-0 to Reserved.............................................................................. 210
• Table 2-76: Changed Value column of Reserved bits 15-0 to 109h............................................................. 210
• Table 2-76: Changed Description of VCLKA4S bit for Value = 8h-Fh .......................................................... 210
• Table 2-78: Changed Description of PLL1_RFSLIP_FILTER_COUNT and PLL1_RFSLIP_FILTER_KEY bits........... 212
• Section 2.5.2.10: Changed paragraph............................................................................................... 214
• Figure 2-68: Corrected register bit fields............................................................................................ 214
• Table 2-81: Changed table to reflect updated register bit fields ................................................................. 214
• Section 2.5.2.11: Changed paragraph............................................................................................... 215
• Figure 2-69: Corrected register bit fields............................................................................................ 215
• Table 2-82: Changed table to reflect updated register bit fields ................................................................. 215