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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
List of Figures
20-56. FTC Interrupt Flag Register (FTCFLAG) [offset = 124h] ............................................................ 749
20-57. LFS Interrupt Flag Register (LFSFLAG) [offset = 12Ch] ............................................................ 750
20-58. HBC Interrupt Flag Register (HBCFLAG) [offset = 134h] ........................................................... 750
20-59. BTC Interrupt Flag Register (BTCFLAG) [offset = 13Ch]............................................................ 751
20-60. FTCA Interrupt Channel Offset Register (FTCAOFFSET) [offset = 14Ch]........................................ 752
20-61. LFSA Interrupt Channel Offset Register (LFSAOFFSET) [offset = 150h]......................................... 753
20-62. HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h] ....................................... 754
20-63. BTCA Interrupt Channel Offset Register (BTCAOFFSET) [offset = 158h] ........................................ 755
20-64. FTCB Interrupt Channel Offset Register (FTCBOFFSET) [offset = 160h] ........................................ 756
20-65. LFSB Interrupt Channel Offset Register (LFSBOFFSET) [offset = 164h]......................................... 757
20-66. HBCB Interrupt Channel Offset Register (HBCBOFFSET) [offset = 168h] ....................................... 758
20-67. BTCB Interrupt Channel Offset Register (BTCBOFFSET) [offset = 16Ch]........................................ 759
20-68. Port Control Register (PTCRL) [offset = 178h] ....................................................................... 760
20-69. RAM Test Control Register (RTCTRL) [offset = 17Ch] .............................................................. 761
20-70. Debug Control Register (DCTRL) [offset = 180h] .................................................................... 762
20-71. Watch Point Register (WPR) [offset = 184h].......................................................................... 763
20-72. Watch Mask Register (WMR) [offset = 188h] ......................................................................... 763
20-73. FIFO A Active Channel Source Address Register (FAACSADDR) [offset = 18Ch].............................. 764
20-74. FIFO A Active Channel Destination Address Register (FAACDADDR) [offset = 190h] ......................... 764
20-75. FIFO A Active Channel Transfer Count Register (FAACTC) [offset = 194h] ..................................... 764
20-76. FIFO B Active Channel Source Address Register (FBACSADDR) [offset = 198h] .............................. 765
20-77. FIFO B Active Channel Destination Address Register (FBACDADDR) [offset = 19Ch]......................... 765
20-78. FIFO B Active Channel Transfer Count Register (FBACTC) [offset = 1A0h] ..................................... 765
20-79. ECC Control Register (DMAPECR) [offset = 1A8h].................................................................. 766
20-80. DMA ECC Error Address Register (DMAPAR) [offset = 1ACh] .................................................... 767
20-81. DMA Memory Protection Control Register 1 (DMAMPCTRL1) [offset = 1B0h]................................... 768
20-82. DMA Memory Protection Status Register 1 (DMAMPST1) [offset = 1B4h] ....................................... 770
20-83. DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) [offset = 1B8h]..................... 771
20-84. DMA Memory Protection Region 0 End Address Register (DMAMPR0E) [offset = 1BCh] ..................... 771
20-85. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) [offset = 1C0h]..................... 772
20-86. DMA Memory Protection Region 1 End Address Register (DMAMPR1E) [offset = 1C4h] ..................... 772
20-87. DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) [offset = 1C8h]..................... 773
20-88. DMA Memory Protection Region 2 End Address Register (DMAMPR2E) [offset = 1CCh] ..................... 773
20-89. DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) [offset = 1D0h]..................... 774
20-90. DMA Memory Protection Region 3 End Address Register (DMAMPR3E) [offset = 1D4h] ..................... 774
20-91. DMA Memory Protection Control Register 2 (DMAMPCTRL2) [offset = 1D8h] .................................. 775
20-92. DMA Memory Protection Status Register 2 (DMAMPST2) [offset = 1DCh]....................................... 777
20-93. DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) [offset = 1E0h]..................... 778
20-94. DMA Memory Protection Region 4 End Address Register (DMAMPR4E) [offset = 1E4h]...................... 778
20-95. DMA Memory Protection Region 5 Start Address Register (DMAMPR5S) [offset = 1E8h]..................... 779
20-96. DMA Memory Protection Region 5 End Address Register (DMAMPR5E) [offset = 1ECh] ..................... 779
20-97. DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) [offset = 1F0h]..................... 780
20-98. DMA Memory Protection Region 6 End Address Register (DMAMPR6E) [offset = 1F4h]...................... 780
20-99. DMA Memory Protection Region 7 Start Address Register (DMAMPR7S) [offset = 1F8h]..................... 781
20-100. DMA Memory Protection Region 7 End Address Register (DMAMPR7E) [offset = 1FCh] .................... 781
20-101. DMA Single-Bit ECC Control Register (DMASECCCTRL) [offset = 228h] ...................................... 782
20-102. DMA ECC Single-Bit Error Address Register (DMAECCSBE) [offset = 230h].................................. 783
20-103. FIFO A Status Register (FIFOASTAT) [offset = 240h] ............................................................. 784
20-104. FIFO B Status Register (FIFOBSTAT) [offset = 244h] ............................................................. 784
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