Texas Instruments TMS570LC4357 - Page 44

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44
SPNU563A–March 2018
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List of Figures
20-7. DMA Indexing Example 1................................................................................................ 704
20-8. DMA Indexing Example 2................................................................................................ 705
20-9. Fixed Priority Scheme.................................................................................................... 705
20-10. Example of Priority Queues ............................................................................................. 706
20-11. Example Channel Assignments......................................................................................... 707
20-12. Example of DMA Data Unpacking...................................................................................... 708
20-13. Example of DMA Data Packing ......................................................................................... 709
20-14. DMA Interrupts ............................................................................................................ 713
20-15. Detailed Interrupt Structure (Frame Transfer Complete Path)...................................................... 713
20-16. Example of Channel Chaining .......................................................................................... 716
20-17. Example of Protection Mechanism ..................................................................................... 718
20-18. DMA Transaction Parity.................................................................................................. 720
20-19. Global Control Register (GCTRL) [offset = 00] ....................................................................... 724
20-20. Channel Pending Register (PEND) [offset = 04h] .................................................................... 725
20-21. DMA Status Register (DMASTAT) [offset = 0Ch] .................................................................... 725
20-22. DMA Revision ID Register (DMAREVID) [offset = 10h] ............................................................. 726
20-23. HW Channel Enable Set and Status Register (HWCHENAS) [offset = 14h] ..................................... 727
20-24. HW Channel Enable Reset and Status Register (HWCHENAR) [offset = 1Ch].................................. 727
20-25. SW Channel Enable Set and Status Register (SWCHENAS) [offset = 24h]...................................... 728
20-26. SW Channel Enable Reset and Status Register (SWCHENAR) [offset = 2Ch] .................................. 728
20-27. Channel Priority Set Register (CHPRIOS) [offset = 34h]............................................................ 729
20-28. Channel Priority Reset Register (CHPRIOR) [offset = 3Ch] ........................................................ 729
20-29. Global Channel Interrupt Enable Set Register (GCHIENAS) [offset = 44h]....................................... 730
20-30. Global Channel Interrupt Enable Reset Register (GCHIENAR) [offset = 4Ch] ................................... 730
20-31. DMA Request Assignment Register 0 (DREQASI0) [offset = 54h] ................................................ 731
20-32. DMA Request Assignment Register 1 (DREQASI1) [offset = 58h] ................................................ 732
20-33. DMA Request Assignment Register 2 (DREQASI2) [offset = 5Ch] ................................................ 733
20-34. DMA Request Assignment Register 3 (DREQASI3) [offset = 60h] ................................................ 734
20-35. DMA Request Assignment Register 4 (DREQASI4) [offset = 64h] ................................................ 735
20-36. DMA Request Assignment Register 5 (DREQASI5) [offset = 68h] ................................................ 736
20-37. DMA Request Assignment Register 6 (DREQASI6) [offset = 6Ch] ................................................ 737
20-38. DMA Request Assignment Register 7 (DREQASI7) [offset = 70h] ................................................ 738
20-39. Port Assignment Register 0 (PAR0) [offset = 94h] ................................................................... 739
20-40. Port Assignment Register 1 (PAR1) [offset = 98h] ................................................................... 740
20-41. Port Assignment Register 2 (PAR2) [offset = 9Ch]................................................................... 741
20-42. Port Assignment Register 3 (PAR3) [offset = A0h]................................................................... 742
20-43. FTC Interrupt Mapping Register (FTCMAP) [offset = B4h].......................................................... 743
20-44. LFS Interrupt Mapping Register (LFSMAP) [offset = BCh].......................................................... 743
20-45. HBC Interrupt Mapping Register (HBCMAP) [offset = C4h]......................................................... 743
20-46. BTC Interrupt Mapping Register (BTCMAP) [offset = CCh]......................................................... 744
20-47. FTC Interrupt Enable Set Register (FTCINTENAS) [offset = DCh] ................................................ 745
20-48. FTC Interrupt Enable Reset (FTCINTENAR) [offset = E4h]......................................................... 745
20-49. LFS Interrupt Enable Set Register (LFSINTENAS) [offset = ECh] ................................................. 746
20-50. LFS Interrupt Enable Reset Register (LFSINTENAR) [offset = F4h] .............................................. 746
20-51. HBC Interrupt Enable Set Register (HBCINTENAS) [offset = FCh]................................................ 747
20-52. HBC Interrupt Enable Reset Register (HBCINTENAR) [offset = 104h]............................................ 747
20-53. BTC Interrupt Enable Set Register (BTCINTENAS) [offset = 10Ch]............................................... 748
20-54. BTC Interrupt Enable Reset Register (BTCINTENAR) [offset = 114h] ............................................ 748
20-55. Global Interrupt Flag Register (GINTFLAG) [offset = 11Ch] ........................................................ 749