Texas Instruments TMS570LC4357 - Page 71

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71
SPNU563A–March 2018
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List of Figures
36-30. DMM Pin Control 8 (DMMPC8) [offset = 8Ch] ...................................................................... 2152
37-1. RAM Trace Port Module Block Diagram ............................................................................. 2156
37-2. Packet Format Trace Mode for RAM Locations..................................................................... 2157
37-3. Packet Format Trace Mode for Peripheral Locations .............................................................. 2157
37-4. Packet Format in Direct Data Mode .................................................................................. 2159
37-5. Example for Trace Region Setup ..................................................................................... 2160
37-6. FIFO Overflow Handling................................................................................................ 2161
37-7. RTP Packet Transfer with Sync Signal............................................................................... 2162
37-8. Packet Format in Trace Mode ......................................................................................... 2162
37-9. RTP Global Control Register (RTPGLBCTRL) (offset = 00h) ..................................................... 2164
37-10. RTP Trace Enable Register (RTPTRENA) (offset = 04h).......................................................... 2167
37-11. RTP Global Status Register (RTPGSR) (offset = 08h)............................................................. 2169
37-12. RTP RAM 1 Trace Region Registers (RTPRAM1REGn) (offset = 0Ch and 10h) .............................. 2171
37-13. RTP RAM 2 Trace Region Registers (RTPRAM2REGn) (offset = 14h and 18h)............................... 2172
37-14. RTP RAM 3 Trace Region Registers (RTPRAM3REGn) (offset = 1Ch and 20h) .............................. 2173
37-15. RTP Peripheral Trace Region Registers (RTPPERREGn) (offset = 24h and 28h)............................. 2175
37-16. RTP Direct Data Mode Write Register (RTPDDMW) (offset = 2Ch) ............................................. 2176
37-17. RTP Pin Control 0 Register (RTPPC0) (offset = 34h).............................................................. 2177
37-18. RTP Pin Control 1 Register (RTPPC1) (offset = 38h).............................................................. 2178
37-19. RTP Pin Control 2 Register (RTPPC2) (offset = 3Ch) ............................................................. 2179
37-20. RTP Pin Control 3 Register (RTPPC3) (offset = 40h).............................................................. 2180
37-21. RTP Pin Control 4 Register (RTPPC4) (offset = 44h).............................................................. 2181
37-22. RTP Pin Control 5 Register (RTPPC5) (offset = 48h).............................................................. 2182
37-23. RTP Pin Control 6 Register (RTPPC6) (offset = 4Ch) ............................................................. 2183
37-24. RTP Pin Control 7 Register (RTPPC7) (offset = 50h).............................................................. 2185
37-25. RTP Pin Control 8 Register (RTPPC8) (offset = 54h).............................................................. 2186
38-1. eFuse Self Test Flow Chart............................................................................................ 2190
38-2. EFC Boundary Control Register (EFCBOUND) [offset = 1Ch].................................................... 2191
38-3. EFC Pins Register (EFCPINS) [offset = 2Ch] ...................................................................... 2193
38-4. EFC Error Status Register (EFCERRSTAT) [offset = 3Ch]........................................................ 2194
38-5. EFC Self Test Cycles Register (EFCSTCY) [offset = 48h] ........................................................ 2194
38-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch]....................................................... 2195