Texas Instruments TMS570LC4357 - Page 72

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72
SPNU563A–March 2018
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List of Tables
List of Tables
2-1. Definition of Terms........................................................................................................ 115
2-2. Module Registers / Memories Memory-Map .......................................................................... 122
2-3. Flash Memory Banks and Sectors...................................................................................... 130
2-4. EPC Registers Bit Mapping ............................................................................................. 133
2-5. PBIST Memory Grouping ................................................................................................ 134
2-6. PBIST Algorithm Mapping ............................................................................................... 136
2-7. Memory Initialization Select Mapping .................................................................................. 138
2-8. Causes of Resets......................................................................................................... 139
2-9. Clock Sources............................................................................................................. 142
2-10. Clock Domains ............................................................................................................ 143
2-11. Typical Low-Power Modes............................................................................................... 145
2-12. Clock Test Mode Options................................................................................................ 147
2-13. EXTCTL_Out_Port Register Field Descriptions ...................................................................... 148
2-14. DCC1 Counter 0 Clock Inputs .......................................................................................... 150
2-15. DCC1 Counter 1 Clock / Signal Inputs................................................................................. 150
2-16. DCC2 Counter 0 Clock Inputs .......................................................................................... 150
2-17. DCC2 Counter 1 Clock / Signal Inputs................................................................................. 150
2-18. Primary System Control Registers ..................................................................................... 151
2-19. SYS Pin Control Register 1 (SYSPC1) Field Descriptions.......................................................... 153
2-20. SYS Pin Control Register 2 (SYSPC2) Field Descriptions.......................................................... 153
2-21. SYS Pin Control Register 3 (SYSPC3) Field Descriptions.......................................................... 154
2-22. SYS Pin Control Register 4 (SYSPC4) Field Descriptions.......................................................... 154
2-23. SYS Pin Control Register 5 (SYSPC5) Field Descriptions.......................................................... 155
2-24. SYS Pin Control Register 6 (SYSPC6) Field Descriptions.......................................................... 155
2-25. SYS Pin Control Register 7 (SYSPC7) Field Descriptions.......................................................... 156
2-26. SYS Pin Control Register 8 (SYSPC8) Field Descriptions.......................................................... 156
2-27. SYS Pin Control Register 9 (SYSPC9) Field Descriptions.......................................................... 157
2-28. Clock Source Disable Register (CSDIS) Field Descriptions ........................................................ 158
2-29. Clock Sources Table ..................................................................................................... 158
2-30. Clock Source Disable Set Register (CSDISSET) Field Descriptions .............................................. 159
2-31. Clock Source Disable Clear Register (CSDISCLR) Field Descriptions............................................ 160
2-32. Clock Domain Disable Register (CDDIS) Field Descriptions ....................................................... 161
2-33. Clock Domain Disable Set Register (CDDISSET) Field Descriptions ............................................. 163
2-34. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions........................................... 165
2-35. GCLK1, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) Field Descriptions ............................ 167
2-36. Peripheral Asynchronous Clock Source Register (VCLKASRC) Field Descriptions............................. 168
2-37. RTI Clock Source Register (RCLKSRC) Field Descriptions ........................................................ 169
2-38. Clock Source Valid Register (CSVSTAT) Field Descriptions ....................................................... 170
2-39. Memory Self-Test Global Control Register (MSTGCR) Field Descriptions ....................................... 171
2-40. Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions...................... 172
2-41. MBIST Controller/Memory Initialization Enable Register (MSINENA) Field Descriptions....................... 173
2-42. MSTC Global Status Register (MSTCGSTAT) Field Descriptions ................................................. 174
2-43. Memory Hardware Initialization Status Register (MINISTAT) Field Descriptions ................................ 175
2-44. PLL Control Register 1 (PLLCTL1) Field Descriptions .............................................................. 176
2-45. PLL Control Register 2 (PLLCTL2) Field Descriptions .............................................................. 177
2-46. SYS Pin Control Register 10 (SYSPC10) Field Descriptions....................................................... 178
2-47. Die Identification Register, Lower Word (DIEIDL) Field Descriptions.............................................. 179