Texas Instruments TMS570LC4357 - Page 74

www.ti.com
74
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
List of Tables
2-97. Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions ....................................... 229
2-98. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions ................... 230
2-99. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions ................... 230
2-100. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) Field Descriptions................. 231
2-101. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNCLR1) Field Descriptions ................... 231
2-102. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) Field Descriptions................................ 232
2-103. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) Field Descriptions................................ 233
2-104. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) Field Descriptions................................ 233
2-105. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) Field Descriptions................................ 234
2-106. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) Field Descriptions ............................. 234
2-107. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) Field Descriptions ............................. 235
2-108. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) Field Descriptions ............................. 235
2-109. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3) Field Descriptions ............................. 236
2-110. Debug Frame Powerdown Set Register (PDPWRDWNSET) Field Descriptions ................................ 236
2-111. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) Field Descriptions.............................. 237
2-112. MasterID Protection Write Enable Register (MSTIDWRENA) Field Descriptions................................ 237
2-113. MasterID Enable Register (MSTIDENA) Field Descriptions ........................................................ 238
2-114. MasterID Diagnostic Control Register (MSTIDDIAGCTRL) Field Descriptions................................... 239
2-115. Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L) Field Descriptions ....................... 240
2-116. Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H) Field Descriptions ...................... 242
2-117. Peripheral Frame n MasterID Protection Register_L/H (PSnMSTID_L/H) Field Descriptions.................. 243
2-118. Privileged Peripheral Frame 0 MasterID Protection Register_L (PPS0MSTID_L) Field Descriptions......... 244
2-119. Privileged Peripheral Frame 0 MasterID Protection Register_H (PPS0MSTID_H) Field Description ......... 245
2-120. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H) Field Descriptions ... 246
2-121. Privileged Peripheral Extended Frame 0 MasterID Protection Register_L (PPSE0MSTID_L) Field
Descriptions ............................................................................................................... 247
2-122. Privileged Peripheral Extended Frame 0 MasterID Protection Register_H (PPSE0MSTID_H) Field
Descriptions ............................................................................................................... 248
2-123. Privileged Peripheral Extended Frame n MasterID Protection Register_L/H (PPSEnMSTID_L/H) Field
Descriptions ............................................................................................................... 249
2-124. Peripheral Memory Frame MasterID Protection Register (PCSnMSTID) Field Descriptions................... 250
2-125. Privileged Peripheral Memory Frame MasterID Protection Register (PPCSnMSTID) Field Descriptions .... 251
3-1. SCM Registers ............................................................................................................ 260
3-2. SCM REVID Register (SCMREVID) Field Descriptions ............................................................. 260
3-3. SCM Control Register (SCMCNTRL) Field Descriptions ............................................................ 261
3-4. SCM Compare Threshold Counter Register (SCMTHRESHOLD) Field Descriptions........................... 262
3-5. SCM Initiator Error0 Status Register (SCMIAERR0STAT) Field Descriptions ................................... 263
3-6. SCM Initiator Error1 Status Register (SCMIAERR1STAT) Field Descriptions ................................... 263
3-7. SCM Initiator Active Status Register (SCMIASTAT) Field Descriptions........................................... 264
3-8. SCM Target Active Status Register (SCMTASTAT) Field Descriptions........................................... 264
4-1. Bus Master / Slave Connectivity for Peripheral Interconnect Subsystem ......................................... 266
4-2. CPU Interconnect Subsystem SDC Register Bit Field Mapping.................................................... 267
4-3. Bus Master / Slave Connectivity for CPU Interconnect Subsystem................................................ 268
4-4. SCM Register Bit Mapping .............................................................................................. 271
4-5. SDC MMR Registers ..................................................................................................... 272
4-6. SDC Status Register (SDC_STATUS) Field Descriptions........................................................... 273
4-7. SDC Control Register (SDC_CONTROL) Field Descriptions....................................................... 274
4-8. Error Generic Parity Register (ERR_GENERIC_PARITY) Field Descriptions.................................... 274
4-9. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) Field Descriptions .................. 275
4-10. Error Transaction ID Register (ERR_TRANS_ID) Field Descriptions.............................................. 275