Texas Instruments TMS570LC4357 - Page 95

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SPNU563A–March 2018
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List of Tables
28-24. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions ..................................................... 1557
28-25. Chip Select Number Active ............................................................................................ 1559
28-26. SPI Receive Buffer Register (SPIBUF) Field Descriptions ........................................................ 1560
28-27. SPI Emulation Register (SPIEMU) Field Descriptions.............................................................. 1562
28-28. SPI Delay Register (SPIDELAY) Field Descriptions................................................................ 1562
28-29. SPI Default Chip Select Register (SPIDEF) Field Descriptions................................................... 1565
28-30. SPI Data Format Registers (SPIFMTn) Field Descriptions ........................................................ 1566
28-31. Transfer Group Interrupt Vector 0 (INTVECT0) ..................................................................... 1568
28-32. Transfer Group Interrupt Vector 1 (INTVECT1) ..................................................................... 1569
28-33. SPI Pin Control Register 9 (SPIPC9) Field Descriptions........................................................... 1571
28-34. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions................................. 1572
28-35. Multi-buffer Mode Enable Register (MIBSPIE) Field Descriptions................................................ 1575
28-36. TG Interrupt Enable Set Register (TGITENST) Field Descriptions ............................................... 1576
28-37. TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions ............................................ 1577
28-38. Transfer Group Interrupt Level Set Register (TGITLVST) Field Descriptions................................... 1578
28-39. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions ................................ 1579
28-40. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions ................................ 1580
28-41. Tick Count Register (TICKCNT) Field Descriptions ................................................................ 1581
28-42. Last TG End Pointer (LTGPEND) Field Descriptions .............................................................. 1582
28-43. TG Control Registers (TGxCTRL) Field Descriptions .............................................................. 1583
28-44. DMA Channel Control Register (DMAxCTRL) Field Descriptions ................................................ 1586
28-45. MibSPI DMAxCOUNT Register (ICOUNT) Field Descriptions .................................................... 1588
28-46. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions ......................................... 1589
28-47. MibSPI Parity/ECC Control Register (PAR_ECC_CTRL) Field Descriptions ................................... 1590
28-48. Parity/ECC Status Register (PAR_ECC_STAT) Field Descriptions .............................................. 1591
28-49. Uncorrectable Parity or Double-Bit ECC Error Address Register - RXRAM (UERRADDR1) Field
Descriptions.............................................................................................................. 1592
28-50. Effect of BIG_ENDIAN Port on UERRADDR1[1:0] Bits ............................................................ 1593
28-51. Uncorrectable Parity or Double-Bit ECC Error Address Register - TXRAM (UERRADDR0) Field
Descriptions.............................................................................................................. 1594
28-52. Effect of BIG_ENDIAN Port on UERRADDR0[1:0] Bits ............................................................ 1595
28-53. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions ...................... 1595
28-54. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions....................................... 1596
28-55. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions........................... 1598
28-56. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions........................... 1600
28-57. ECC Diagnostic Control Register (ECCDIAG_CTRL) Field Descriptions........................................ 1601
28-58. ECC Diagnostic Status Register (ECCDIAG_STAT) Field Descriptions......................................... 1602
28-59. Single-Bit Error Address Register - RXRAM (SBERRADDR1) Field Descriptions ............................. 1603
28-60. Single-Bit Error Address Register - TXRAM (SBERRADDR0) Field Descriptions.............................. 1604
28-61. Multi-buffer RAM Register.............................................................................................. 1606
28-62. Multi-buffer RAM Transmit Data Register (TXRAM) Field Descriptions ......................................... 1607
28-63. Chip Select Number Active ............................................................................................ 1609
28-64. Multi-buffer Receive Buffer Register (RXRAM) Field Descriptions ............................................... 1610
29-1. Superfractional Bit Modulation for SCI Mode (Normal Configuration) ........................................... 1629
29-2. Superfractional Bit Modulation for SCI Mode (Maximum Configuration) ........................................ 1630
29-3. SCI Mode (Minimum Configuration) .................................................................................. 1630
29-4. SCI/LIN Interrupts ....................................................................................................... 1637
29-5. Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than 1.3..................... 1644
29-6. Response Length with SCIFORMAT[18:16] Programming ........................................................ 1644