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Peripheral Frames
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SPRUI07–March 2020
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System Control and Interrupts
Table 1-104. REVID Register Field Descriptions (continued)
Bits Field Value Description
0x0001 Silicon Revision 1 - TMS
1.5.4 Write-Followed-by-Read Protection
The PROTSTART and PROTRANGE registers set the memory address range for which CPU "write"
followed by "read" operations are protected (operations occur in sequence rather then in their natural
pipeline order). This is necessary protection for certain peripheral operations.
Example: The following lines of code perform a write to register 1 (REG1) location and then the next
instruction performs a read from Register 2 (REG2) location. On the processor memory bus, with block
protection disabled, the read operation is issued before the write as shown.
MOV @REG1,AL ---------+ TBIT
@REG2,#BIT_X ---------|-------> Read
+-------> Write
If block protection is enabled, then the read is stalled until the write occurs as shown:
MOV @REG1,AL ---------+ TBIT
@REG2,#BIT_X ---------|-----+
+-----|---> Write
+---> Read
(1)
The default values of these registers on reset are selected to cover the Peripheral Frame 1, Peripheral Frame 2, Peripheral
Frame 3, and XINTF Zone 1 areas of the memory map (address range 0x4000 to 0x8000).
Table 1-105. PROTSTART and PROTRANGE Registers
Name Address Size Type Reset Description
PROTSTART 0x0884 16 R/W 0x0100
(1)
The PROTSTART register sets the starting address
relative to the 16 most significant bits of the
processors lower 22-bit address reach. Hence, the
smallest resolution is 64 words.
PROTRANGE 0x0885 16 R/W 0x00FF
(1)
The PROTRANGE register sets the block size (from
the starting address), starting with 64 words and
incrementing by binary multiples (64, 128, 256, 512,
1K, 2K, 4K, 8K, 16K, ...., 2M).
(1)
The quickest way to calculate register value is to divide the desired block starting address by 64.
Table 1-106. PROTSTART Valid Values
Register Bits
(1)
Start Address Register Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 0000 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x00 0040 0x0001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0x00 0080 0x0002 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0x00 00C0 0x0003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
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0x3F FF00 0xFFFC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
0x3F FF40 0xFFFD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
0x3F FF80 0xFFFE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0x3F FFC0 0xFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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