Peripheral Interrupt Expansion (PIE)
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SPRUI07–March 2020
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System Control and Interrupts
Table 1-122. External NMI Interrupt Control Register (XNMICR) Field Descriptions
Bits Field Value Description
15-4 Reserved Reads return zero; writes have no effect.
3-2 Polarity This read/write bit determines whether interrupts are generated on the rising edge or the
falling edge of the signal on the pin.
00 Interrupt generated on a falling edge (high-to-low transition)
01 Interrupt generated on a rising edge low-to-high transition)
10 Interrupt is generated on a falling edge (high to low transition)
11 Interrupt generated on both a falling edge and a rising edge (high to low and low to high
transition)
1 Select Select the source for INT13
0 Timer 1 connected To INT13
1 XNMI_XINT13 connected To INT13
0 Enable This read/write bit enables or disables external interrupt NMI
0 Disable XNMI interrupt
1 Enable XNMI interrupt
The XNMI Control Register (XNMICR) can be used to enable or disable the NMI interrupt to the CPU. In
addition, you can select the source for the INT13 CPU interrupt. The source of the INT13 interrupt can be
either the internal CPU Timer1 or the external GPIO signal assigned to XNMI.
The INT13 interrupt can be connected to XNMI_XINT13 for customer use.
Table 1-123 shows the relationship between the XNMICR Register settings and the interrupt sources to
the 28x CPU.
Table 1-123. XNMICR Register Settings and Interrupt Sources
XNMICR Register Bits 28x CPU Interrupt Timestamp
ENABLE SELECT NMI Source INT13 Source (XNMICTR)
0 0 Disabled CPU Timer 1 None
0 1 Disabled XNMI None
1 0 XNMI CPU Timer 1 XNMI
1 1 Disabled XNMI XNMI
1.6.5.3 External Interrupt 1 Counter (XINT1CTR) (Address 7078h)
For XINT1 and XINT2, there is also a 16-bit counter that is reset to 0x000 whenever an interrupt edge is
detected. These counters can be used to accurately time stamp an occurrence of the interrupt.
Figure 1-93. External Interrupt 1 Counter (XINT1CTR) (Address 7078h)
15 0
INTCTR[15-0]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-124. External Interrupt 1 Counter (XINT1CTR) Field Descriptions
Bits Field Description
15-0 INTCTR This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The counter value is
reset to 0x0000 when a valid interrupt edge is detected and then continues counting until the next valid
interrupt edge is detected. When the interrupt is disabled, the counter stops. The counter is a free-running
counter and wraps around to zero when the max value is reached. The counter is a read only register and
can only be reset to zero by a valid interrupt edge or by reset.
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