FSG
CLKG
19181716151413121110987654321
Frame-synchronization period: (FPER+1) x CLKG
Frame-synchronization pulse width: (FWID + 1) x CLKG
Transmitter Configuration
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Multichannel Buffered Serial Port (McBSP)
Figure 12-58. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Falling Edge
12.9.18 SRG Frame-Synchronization Period and Pulse Width
Table 12-66 shows which register bits set the SRG Frame-Synchronization Period and Pulse Width.
Table 12-66. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width
Register Bit Name Function Type Reset Value
SRGR2 11-0 FPER Sample rate generator frame-synchronization period R/W 0000 0000 0000
For the frame-synchronization signal FSG, (FPER + 1)
determines the period from the start of a frame-
synchronization pulse to the start of the next frame-
synchronization pulse.
Range for (FPER + 1): 1 to 4096 CLKG cycles.
SRGR1 15-8 FWID Sample rate generator frame-synchronization pulse width R/W 0000 0000
This field plus 1 determines the width of each frame-
synchronization pulse on FSG.
Range for (FWID + 1): 1 to 256 CLKG cycles.
12.9.18.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization signal, FSG. If
the sample rate generator is supplying receive or transmit frame synchronization, you must program the
bit fields FPER and FWID.
On FSG, the period from the start of a frame-synchronization pulse to the start of the next pulse is (FPER
+ 1) CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG cycles,
which allows up to 4096 data bits per frame. When GSYNC = 1, FPER is a don't care value.
Each pulse on FSG has a width of (FWID + 1) CLKG cycles. The eight bits of FWID allow a pulse width of
1 to 256 CLKG cycles. It is recommended that FWID be programmed to a value less than the
programmed word length.
The values in FPER and FWID are loaded into separate down-counters. The 12-bit FPER counter counts
down the generated clock cycles from the programmed value (4095 maximum) to 0. The 8-bit FWID
counter counts down from the programmed value (255 maximum) to 0.
Figure 12-59 shows a frame-synchronization period of 16 CLKG periods (FPER = 15 or 00001111b) and a
frame-synchronization pulse with an active width of 2 CLKG periods (FWID = 1).
Figure 12-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
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