I2C Module Operational Details
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SPRUI07–March 2020
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Inter-Integrated Circuit Module (I2C)
Table 11-2. Operating Modes of the I2C Module (continued)
Operating Mode Description
Master-receiver mode The I2C module is a master and receives data from a slave.
This mode can be entered only from the master-transmitter mode; the I2C module must first
transmit a command to the slave. When you are using any of the 7-bit/10-bit addressing
formats, the I2C module enters its master-receiver mode after transmitting the slave address
byte and R/W = 1. Serial data bits on SDA are shifted into the I2C module with the clock pulses
generated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low when
the intervention of the device is required (RSFULL = 1 in I2CSTR) after a byte has been
received.
Master-transmitter modes The I2C module is a master and transmits control information and data to a slave.
All masters begin in this mode. In this mode, data assembled in any of the 7-bit/10-bit
addressing formats is shifted out on SDA. The bit shifting is synchronized with the clock pulses
generated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low when
the intervention of the device is required (XSMT = 0 in I2CSTR) after a byte has been
transmitted.
To summarize, SCL will be held low in the following conditions:
• When an overrun condition is detected (RSFULL = 1), in Slave-receiver mode.
• When an underflow condition is detected (XSMT = 0), in Slave-transmitter mode.
I2C slave nodes have to accept and provide data when the I2C master node requests it.
• To release SCL in slave-receiver mode, read data from I2CDRR.
• To release SCL in slave-transmitter mode, write data to I2CDXR.
• To force a release without handling the data, reset the module using the I2CMDR.IRS bit.
(1)
S = START condition; A = Address; D = Data byte; P = STOP condition;
Table 11-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of
I2CMDR
RM STT STP Bus Activity
(1)
Description
0 0 0 None No activity
0 0 1 P STOP condition
0 1 0 S-A-D..(n)..D. START condition, slave address, n data bytes (n = value in
I2CCNT)
0 1 1 S-A-D..(n)..D-P START condition, slave address, n data bytes, STOP condition (n =
value in I2CCNT)
1 0 0 None No activity
1 0 1 P STOP condition
1 1 0 S-A-D-D-D. Repeat mode transfer: START condition, slave address, continuous
data transfers until STOP condition or next START condition
1 1 1 None Reserved bit combination (No activity)
11.3.4 I2C Module START and STOP Conditions
START and STOP conditions can be generated by the I2C module when the module is configured to be a
master on the I2C bus. As shown in Figure 11-6:
• The START condition is defined as a high-to-low transition on the SDA line while SCL is high. A
master drives this condition to indicate the start of a data transfer.
• The STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. A master
drives this condition to indicate the end of a data transfer.
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