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Receiver Configuration
717
SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
12.8.21 SRG Clock Mode (Choose an Input Clock)
Table 12-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
Register Bit Name Function Type
Reset
Value
PCR 7 SCLKME Sample rate generator clock mode R/W 0
SRGR2 13 CLKSM R/W 1
SCLKME = 0
Reserved
CLKSM = 0
SCLKME = 0 Sample rate generator clock derived from
LSPCLK (default)
CLKSM = 1
SCLKME = 1 Sample rate generator clock derived from MCLKR
pin
CLKSM = 0
SCLKME = 1 Sample rate generator clock derived from MCLKX
pin
CLKSM = 1
12.8.21.1 SRG Clock Mode
The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or
both, but CLKG is derived from an input clock. Table 12-45 shows the four possible sources of the input
clock. For more details on generating CLKG, see Section 12.4.1.1.
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