I2C Registers
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SPRUI07–March 2020
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Inter-Integrated Circuit Module (I2C)
11.6.2.8 I2CSAR Register (Offset = 7h) [reset = 3FFh]
I2CSAR is shown in Figure 11-25 and described in Table 11-17.
Return to the Summary Table.
The I2C slave address register (I2CSAR) is a 16-bit register for storing the next slave address that will be
transmitted by the I2C module when it is a master. The SAR field of I2CSAR contains a 7-bit or 10-bit
slave address. When the I2C module is not using the free data format (FDF = 0 in I2CMDR), it uses this
address to initiate data transfers with a slave, or slaves. When the address is nonzero, the address is for a
particular slave. When the address is 0, the address is a general call to all slaves. If the 7-bit addressing
mode is selected (XA = 0 in I2CMDR), only bits 6-0 of I2CSAR are used
write 0s to bits 9-7.
Figure 11-25. I2CSAR Register
15 14 13 12 11 10 9 8
RESERVED SAR
R-0h R/W-3FFh
7 6 5 4 3 2 1 0
SAR
R/W-3FFh
Table 11-17. I2CSAR Register Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R 0h
Reserved
9-0 SAR R/W 3FFh
In 7-bit addressing mode (XA = 0 in I2CMDR):
00h-7Fh Bits 6-0 provide the 7-bit slave address that the I2C module
transmits when it is in the master-transmitter
mode. Write 0s to bits 9-7.
In 10-bit addressing mode (XA = 1 in I2CMDR):
000h-3FFh Bits 9-0 provide the 10-bit slave address that the I2C
module transmits when it is in the master transmitter mode.
Reset type: SYSRSn
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