Texas Instruments TMS320 2833 Series User Manual

valid
valid
Lead
Active
Trail
1XTIMCLK
3XTIMCLK
SYSCLKOUT
XTIMCLK
(/1 Mode)
XCLKOUT
(/1 Mode)
XCLKOUT
(/2 Mode)
XRD
XREADY
(synch)
XREADY
(asynch)
XA(19:0)
XZCSx
XD(15:0)
or XD(31:0)
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SPRUI07–March 2020
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External Interface (XINTF)
Figure 14-13. Generic Read Cycle (XTIMCLK = SYSCLKOUT mode)
A XRDLEAD = 2, XRDACTIVE = 4, XRDTRAIL = 2
The XREADY signal can be sampled synchronously or asynchronously or ignored by each zone. If it is
sampled synchronously, then the XREADY signal MUST meet set-up and hold timing relative to one
XTIMCLK edge before the end of the active period. If it is sampled asynchronously, then the XREADY
signal MUST meet set-up and hold timing relative to three XTIMCLK edges before the end of the active
period. If XREADY is low at the sampling interval, an extra XTIMCLK period is added to the active phase
and the XREADY input is sampled again on the next rising edge of XTIMCLK. XCLKOUT has no effect on
the sampling interval.

Texas Instruments TMS320 2833 Series Specifications

General

Brand	Texas Instruments
Model	TMS320 2833 Series
Category	Controller
Language	English