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Peripheral Interrupt Expansion (PIE)
165
SPRUI07–March 2020
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System Control and Interrupts
1.6.5.4 External Interrupt 2 Counter (XINT2CTR) (Address 7079h)
For XINT1 and XINT2, there is also a 16-bit counter that is reset to 0x000 whenever an interrupt edge is
detected. These counters can be used to accurately time stamp an occurrence of the interrupt.
Figure 1-94. External Interrupt 2 Counter (XINT2CTR) (Address 7079h)
15 0
INTCTR[15-0]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-125. External Interrupt 2 Counter (XINT2CTR) Field Descriptions
Bits Field Description
15-0 INTCTR This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The counter value is
reset to 0x0000 when a valid interrupt edge is detected and then continues counting until the next valid
interrupt edge is detected. When the interrupt is disabled, the counter stops. The counter is a free-running
counter and wraps around to zero when the max value is reached. The counter is a read only register and
can only be reset to zero by a valid interrupt edge or by reset.
1.6.5.5 External NMI Interrupt Counter (XNMICTR) (Address 707Fh)
Figure 1-95. External NMI Interrupt Counter (XNMICTR) (Address 707Fh)
15 0
INTCTR[15-0]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-126. External NMI Interrupt Counter (XNMICTR) Field Descriptions
Bits Field Description
15-0 INTCTR This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The counter value is
reset to 0x0000 when a valid interrupt edge is detected and then continues counting until the next valid
interrupt edge is detected. When the interrupt is disabled, the counter stops. The counter is a free-running
counter and wraps around to zero when the max value is reached. The counter is a read only register and
can only be reset to zero by a valid interrupt edge or by reset.
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