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Texas Instruments TMS320 2833 Series User Manual

Texas Instruments TMS320 2833 Series
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eCAN Registers
825
SPRUI07March 2020
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Copyright © 2020, Texas Instruments Incorporated
Controller Area Network (CAN)
13.8.18 Timer Management Unit
Several functions are implemented in the eCAN to monitor the time when messages are
transmitted/received. A separate state machine is included in the eCAN to handle the time-control
functions. This state machine has lower priority when accessing the registers than the CAN state machine
has. Therefore, the time-control functions may be delayed by other ongoing actions.
13.8.18.1 Time Stamp Functions
To get an indication of the time of reception or transmission of a message, a free-running 32-bit timer
(TSC) is implemented in the module. Its content is written into the time stamp register of the
corresponding mailbox (Message Object Time Stamp [MOTS]) when a received message is stored or a
message has been transmitted.
The counter is driven from the bit clock of the CAN bus line. The timer is stopped during the initialization
mode or if the module is in sleep or suspend mode. After power-up reset, the free-running counter is
cleared.
The most significant bit of the TSC register is cleared by writing a 1 to TCC (CANMC.14). The TSC
register can also be cleared when mailbox 16 transmitted or received (depending on the setting of
CANMD.16 bit) a message successfully. This is enabled by setting the MBCC bit (CANMC.15). Therefore,
it is possible to use mailbox 16 for global time synchronization of the network. The CPU can read and
write the counter.
Overflow of the counter is detected by the TSC-counter-overflow-interrupt flag (TCOFn-CANGIFn.16). An
overflow occurs when the highest bit of the TSC counter changes to 1. Therefore, the CPU has enough
time to handle this situation.
13.8.18.1.1 Time-Stamp Counter Register (CANTSC)
This register holds the time-stamp counter value at any instant of time. This is a free-running 32-bit timer
which is clocked by the bit clock of the CAN bus. For example, at a bit rate of 1 Mbps, CANTSC would
increment every 1 μs.
Figure 13-33. Time-Stamp Counter Register (CANTSC)
31 0
TSC31:0
R/WP-0
LEGEND: R = Read; WP = Write in EALLOW enabled mode only; -n = value after reset
Note: eCAN mode only, reserved in the SCC
Table 13-29. Time-Stamp Counter Register (CANTSC) Field Descriptions
Bit Field Value Description
31:0 TSC31:0 Time-stamp counter register. Value of the local network time counter used for the time-stamp and
time-out functions.

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Texas Instruments TMS320 2833 Series Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320 2833 Series
CategoryController
LanguageEnglish

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