Registers
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SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
Figure 3-87. Event-Trigger Clear Register (ETCLR)
15 8
Reserved
R = 0
7 4 3 2 1 0
Reserved SOCB SOCA Reserved INT
R-0 R/W-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-47. Event-Trigger Clear Register (ETCLR) Field Descriptions
Bits Name Value Description
15-4 Reserved Reserved
3 SOCB ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[SOCB] flag bit
2 SOCA ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[SOCA] flag bit
1 Reserved Reserved
0 INT ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated
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