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Registers
323
SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
Table 3-45. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued)
Bits Name Description
1-0 INTPRD ePWM Interrupt (EPWMx_INT) Period Select
These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt
is generated. To be generated, the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt
status flag is set from a previous interrupt (ETFLG[INT] = 1) then no interrupt will be generated until
the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to be pending while another
is still being serviced. Once the interrupt is generated, the ETPS[INTCNT] bits will automatically be
cleared.
Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is
enabled and the status flag is clear.
Writing a INTPRD value that is less than the current counter value will result in an undefined state.
If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written,
the counter is incremented.
00 Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.
01 Generate an interrupt on the first event INTCNT = 01 (first event)
10 Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
11 Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
Figure 3-86. Event-Trigger Flag Register (ETFLG)
15 8
Reserved
R-0
7 4 3 2 1 0
Reserved SOCB SOCA Reserved INT
R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-46. Event-Trigger Flag Register (ETFLG) Field Descriptions
Bits Name Value Description
15-4 Reserved Reserved
3 SOCB Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag
0 Indicates no EPWMxSOCB event occurred
1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB
output will continue to be generated even if the flag bit is set.
2 SOCA Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag
Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue to pulse even if the flag bit is
set.
0 Indicates no event occurred
1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA
output will continue to be generated even if the flag bit is set.
1 Reserved Reserved
0 INT Latched ePWM Interrupt (EPWMx_INT) Status Flag
0 Indicates no event occurred
1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be
generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG[INT] bit
is still set. If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared.
Refer to Figure 3-42.
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