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eCAN Registers
821
SPRUI07–March 2020
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Controller Area Network (CAN)
Table 13-23. Global Interrupt Mask Register (CANGIM) Field Descriptions (continued)
Bit Field Value Description
7:3 Reserved Reads are undefined and writes have no effect.
2 GIL Global interrupt level for the interrupts TCOF, WDIF, WUIF, BOIF, EPIF, RMLIF, AAIF and WLIF.
1 All global interrupts are mapped to the ECAN1INT interrupt line.
0 All global interrupts are mapped to the ECAN0INT interrupt line.
1 I1EN Interrupt 1 enable
1 This bit globally enables all interrupts for the ECAN1INT line if the corresponding masks are set.
0 The ECAN1INT interrupt line is disabled.
0 I0EN Interrupt 0 enable
1 This bit globally enables all interrupts for the ECAN0INT line if the corresponding masks are set.
0 The ECAN0INT interrupt line is disabled.
13.8.15.3 Mailbox Interrupt Mask Register (CANMIM)
There is one interrupt flag available for each mailbox. This can be a receive or a transmit interrupt
depending on the configuration of the mailbox. This register is EALLOW protected.
Figure 13-28. Mailbox Interrupt Mask Register (CANMIM)
31 0
MIM.31:0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-24. Mailbox Interrupt Mask Register (CANMIM) Field Descriptions
Bit Field Value Description
31:0 MIM.31:0 Mailbox interrupt mask. After power up all interrupt mask bits are cleared and the interrupts are
disabled. These bits allow any mailbox interrupt to be masked individually.
1 Mailbox interrupt is enabled. An interrupt is generated if a message has been transmitted
successfully (in case of a transmit mailbox) or if a message has been received without any error (in
case of a receive mailbox).
0 Mailbox interrupt is disabled.
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