McBSP Operation
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
length, see Section 12.9.9.
NOTE: If both DXRs are needed (word length larger than 16 bits), the CPU or the DMA controller
must load DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both
DXRs are copied to the transmit shift registers (XSRs), as described in the next step. If
DXR2 is not loaded first, the previous content of DXR2 is passed to the XSR2.
2. When new data arrives in DXR1, the McBSP copies the content of the data transmit register(s) to the
transmit shift register(s). In addition, the transmit ready bit (XRDY) is set. This indicates that the
transmitter is ready to accept new data from the CPU or the DMA controller.
If the word length is 16 bits or smaller, only XSR1 is used. If the word length is larger than 16 bits,
XSR2 and XSR1 are used and XSR2 contains the most significant bits.
If companding is used during the transfer (XCOMPAND = 10b or 11b in XCR2), the McBSP
compresses the 16-bit data in DXR1 to 8-bit data in the μ-law or A-law format in XSR1. If companding
is disabled, the McBSP passes data from the DXR(s) to the XSR(s) without modification.
3. The McBSP waits for a transmit frame-synchronization pulse on internal FSX.
4. When the pulse arrives, the McBSP inserts the appropriate data delay that is selected with the
XDATDLY bits of XCR2.
In the preceding timing diagram (Figure 12-16), a 1-bit data delay is selected.
5. The McBSP shifts data bits from the transmit shift register(s) to the DX pin.
When activity is not properly timed, errors can occur. See the following topics for more details:
• Overwrite in the Transmitter ( Section 12.5.4)
• Underflow in the Transmitter (Section 12.5.5)
• Unexpected Transmit Frame-Synchronization Pulse (Section 12.5.6)
12.3.7 Interrupts and DMA Events Generated by a McBSP
The McBSP sends notification of important events to the CPU and DMA via the internal signals shown in
Table 12-3.
Table 12-3. Interrupts and DMA Events Generated by a McBSP
Internal Signal Description
RINT Receive interrupt
The McBSP sends a receive interrupt request to the CPU based upon a selected condition in the receiver of
the McBSP (a condition selected by the RINTM bits of SPCR1).
XINT Transmit interrupt
The McBSP sends a transmit interrupt request to the CPU based upon a selected condition in the transmitter
of the McBSP (a condition selected by the XINTM bits of SPCR2).
REVT Receive synchronization event
An REVT signal is sent to the DMA when data has been received in the data receive registers (DRRs).
XEVT Transmit synchronization event
An XEVT signal is sent to the DMA when the data transmit registers (DXRs) are ready to accept the next
serial word for transmission.
12.4 McBSP Sample Rate Generator
Each McBSP contains a sample rate generator (SRG) that can be programmed to generate an internal
data clock (CLKG) and an internal frame-synchronization signal (FSG). CLKG can be used for bit shifting
on the data receive (DR) pin and/or the data transmit (DX) pin. FSG can be used to initiate frame transfers
on DR and/or DX. Figure 12-17 is a conceptual block diagram of the sample rate generator.
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