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I2C Registers
639
SPRUI07–March 2020
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Inter-Integrated Circuit Module (I2C)
Table 11-12. I2CSTR Register Field Descriptions (continued)
Bit Field Type Reset Description
1 NACK R/W1C 0h
No-acknowledgment interrupt flag bit.
NACK applies when the I2C module is a transmitter (master or
slave). NACK indicates whether the I2C module has detected an
acknowledge bit (ACK) or a noacknowledge bit (NACK) from the
receiver. The CPU can poll NACK or use the NACK interrupt
request.
Reset type: SYSRSn
0h (R/W) = ACK received/NACK not received. This bit is cleared by
any one of the following events:
- An acknowledge bit (ACK) has been sent by the receiver.
- NACK is manually cleared. To clear this bit, write a 1 to it.
- The CPU reads the interrupt source register (I2CISRC) and the
register contains the code for a NACK interrupt. Emulator reads of
the I2CISRC do not affect this bit.
- The I2C module is reset.
1h (R/W) = NACK bit received. The hardware detects that a no-
acknowledge (NACK) bit has been received.
Note: While the I2C module performs a general call transfer, NACK
is 1, even if one or more slaves send acknowledgment.
0 ARBL R/W1C 0h
Arbitration-lost interrupt flag bit (only applicable when the I2C
module is a master-transmitter).
ARBL primarily indicates when the I2C module has lost an arbitration
contest with another mastertransmitter. The CPU can poll ARBL or
use the ARBL interrupt request.
Reset type: SYSRSn
0h (R/W) = Arbitration not lost. AL is cleared by any one of the
following events:
- AL is manually cleared. To clear this bit, write a 1 to it.
- The CPU reads the interrupt source register (I2CISRC) and the
register contains the code for an
AL interrupt. Emulator reads of the I2CISRC do not affect this bit.
- The I2C module is reset.
1h (R/W) = Arbitration lost. AL is set by any one of the following
events:
- The I2C module senses that it has lost an arbitration with two or
more competing transmitters that started a transmission almost
simultaneously.
- The I2C module attempts to start a transfer while the BB (bus
busy) bit is set to 1.
When AL becomes 1, the MST and STP bits of I2CMDR are
cleared, and the I2C module becomes a slave-receiver.
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