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Bootloader Features
173
SPRUI07–March 2020
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Boot ROM
2.2.2 Bootloader Device Configuration
At reset, the device is in 27x™ object-compatible mode. It is up to the application to place the device in
the proper operating mode before execution proceeds.
When booting from the internal boot ROM, the device is configured for 28x operating mode by the boot
ROM software. You are responsible for any additional configuration required.
For example, if your application includes C2xLP™ source, then you are responsible for configuring the
device for C2xLP source compatibility prior to execution of code generated from C2xLP source.
The configuration required for each operating mode is summarized in Table 2-2.
(1)
C27x refers to the TMS320C27x family of processors. C2xLP refers to the
TMS320F24x/TMS320LF240xA family of devices that incorporate the C2xLP core. The information in
the table above is for reference only and is not applicable for the typical user development. For more
information on the C2xLP core, refer to SPRU430.
(2)
Normally for C27x compatibility, the M0M1MAP would be 0. On these devices, however, it is tied off
high internally; therefore, at reset, M0M1MAP is always configured for 28x mode.
Table 2-2. Configuration for Device Modes
(1)
C27x Mode (Reset) 28x Mode
C2xLP Source
Compatible Mode
OBJMODE 0 1 1
AMODE 0 0 1
PAGE0 0 0 0
M0M1MAP
(2)
1 1 1
Other Settings SXM = 1, C = 1, SPM = 0
2.2.3 PLL Multiplier and DIVSEL Selection
The Boot ROM changes the PLL multiplier (PLLCR) and divider (PLLSTS[DIVSEL]) bits as follows:
• XINTF parallel loader:
– PLLCR and PLLSTS[DIVSEL] are specified by the user as part of the incoming data stream.
• All other boot modes:
– PLLCR is not modified. PLLSTS[DIVSEL] is set to 2 for SYSCLKOUT = CLKIN/2 . This increases
the speed of the loaders.
NOTE: The PLL multiplier (PLLSTS) and divider (PLLSTS[DIVSEL]) are not affected by a reset from
the debugger. Therefore, a boot that is initialized from a reset from Code Composer Studio™
may be at a different speed than booting by pulling the external reset line (XRS) low.
The reset value of PLLSTS[DIVSEL] is 0. This configures the device for SYSCLKOUT =
CLKIN/4 . The boot ROM will change this to SYSCLKOUT = CLKIN/2 to improve
performance of the loaders. PLLSTS[DIVSEL] is left in this state when the boot ROM exits
and it is up to the application to change it before configuring the PLLCR register.
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