APRD
TSCTR
FFFFFFFF
ACMP
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
1000h
500h
300h
Capture Mode Description
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SPRUI07–March 2020
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Enhanced Capture (eCAP)
• The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators.
• When CAP1/2 registers are not used in capture mode, their contents can be used as Period and
Compare values in APWM mode.
• Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4). The shadow register
contents are transferred over to CAP1/2 registers, either immediately upon a write, or on a CTR = PRD
trigger.
• In APWM mode, writing to CAP1/CAP2 active registers will also write the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 will invoke the shadow mode.
• During initialization, you must write to the active registers for both period and compare. This
automatically copies the initial values into the shadow values. For subsequent compare updates,
during run-time, you only need to use the shadow registers.
Figure 5-10. PWM Waveform Details Of APWM Mode Operation
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