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Signal Descriptions
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SPRUI07–March 2020
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External Interface (XINTF)
14.7 Signal Descriptions
Table 14-20. XINTF Signal Descriptions
Name Type Description
XD(31:0) I/O/Z Bidirectional 32-bit data bus. In 16-bit mode only XD(15:0) are used.
XA(31:1) O/Z Address bus. The address is placed on the bus on the rising edge of XCLKOUT and
held on the bus until the next access.
Specific devices may not have all 32 address lines. See the data sheet for a specific
device.
XA0/ XWE1 O/Z
In 16-bit data mode (see ), this signal is the least significant address line (XA0).
In 32-bit data mode, this signal is the active low write strobe XWE1. XWE1 is used,
along with XWE0, for 32-bit bus operation as shown in Section 14.2.7.
XCLKOUT O/Z Single output clock derived from the XTIMCLK to be used for on-chip and off-chip
wait-state generation and as a general-purpose clock source. XCLKOUT is either the
same frequency or ½ the frequency of XTIMCLK, as defined by the CLKMODE bit in
the XINTCNF2 register. At reset
XCLKOUT = XTIMCLK/2
XTIMCLK = SYSCLKOUT/2
XWE0 O/Z Active low write strobe. In 16-bit mode, this signal is driven low on all bus modes and
data size types. In 32-bit mode, it is driven as shown in Figure 14-5. The write strobe
waveform is specified, per zone basis, by the Lead, Active, Trail periods in the
XTIMINGx registers.
XRD O/Z Active low read strobe. This signal is driven low on all bus modes and data size types.
The read strobe waveform is specified, per zone basis, by the Lead, Active, Trail
periods in the XTIMINGx registers.
Note: The XRD and XWE0 signals are mutually exclusive.
XR/W O/Z Read-not-write control. When high, this signal indicates a read cycle is active, when
low, it indicates a write cycle is active. This signal is normally held high. The XR/W
signal performs similar functions to the XRD and XWE0 signals. Generally, users opt
to use XWE0 and XWE1 because they are cleaner and easier to use.
XZCS0
XZCS6
XZCS7
O Zone chip-selects. These signals are active when an access to the addressed zone is
performed.
XREADY I Indicates peripheral is READY to complete the access when asserted to 1. For each
XINTF zone, this can be configured to be a synchronous or an asynchronous input. In
synchronous mode, the XINTF interface block requires XREADY to be valid one
XTIMCLK clock cycle before the end of the active period. In asynchronous mode, The
XINTF interface block samples XREADY three XTIMCLK clock cycles before the end
of the active period. XREADY is sampled at the XTIMCLK rate independent of the
XCLKOUT mode.
XHOLD I This signal, when active low, requests the XINTF to release the external bus (place all
busses and strobes into high-impedance state). The XINTF releases the bus when
any current access is complete and there are no pending accesses on the XINTF.
This signal is an asynchronous input and is synchronized by XTIMCLK.
XHOLDA O/Z This signal is driven active low, when the XINTF has granted an XHOLD request. All
XINTF busses and strobe signals will be in a high-impedance state. This signal is
released when the XHOLD signal is released. External devices should only drive the
external bus when this signal is active low.
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