Transmitter Configuration
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
12.9.16 Transmit Frame-Synchronization Mode
Table 12-63 shows which register bits enable the Transmit Frame-Synchronization Mode.
Table 12-63. Register Bits Used to Set the Transmit Frame-Synchronization Mode
Register Bit Name Function Type
Reset
Value
PCR 11 FSXM Transmit frame-synchronization mode R/W 0
FSXM = 0 Transmit frame synchronization is supplied by an
external source via the FSX pin.
FSXM = 1 Transmit frame synchronization is supplied by the
McBSP, as determined by the FSGM bit of SRGR2.
SRGR2 12 FSGM Sample rate generator transmit frame-synchronization mode R/W 0
Used when FSXM = 1 in PCR.
FSGM = 0 The McBSP generates a transmit frame-
synchronization pulse when the content of DXR[1,2] is
copied to XSR[1,2].
FSGM = 1 The transmitter uses frame-synchronization pulses
generated by the sample rate generator. Program the
FWID bits to set the width of each pulse. Program the
FPER bits to set the frame-synchronization period.
Table 12-64 shows how FSXM and FSGM select the source of transmit frame-synchronization pulses. The
three choices are:
• External frame-synchronization input
• Sample rate generator frame-synchronization signal (FSG)
• Internal signal that indicates a DXR-to-XSR copy has been made
Table 12-64 also shows the effect of each bit setting on the FSX pin. The polarity of the signal on the FSX
pin is determined by the FSXP bit.
Table 12-64. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses
FSXM FSGM
Source of Transmit Frame
Synchronization FSX Pin Status
0 0 or 1 An external frame-synchronization signal enters the
McBSP through the FSX pin. The signal is then
inverted by FSXP before being used as internal FSX.
Input
1 1 Internal FSX is driven by the sample rate generator
frame-synchronization signal (FSG).
Output. FSG is inverted by FSXP before being driven
out on FSX pin.
1 0 A DXR-to-XSR copy causes the McBSP to generate a
transmit frame-synchronization pulse that is 1 cycle
wide.
Output. The generated frame-synchronization pulse is
inverted as determined by FSXP before being driven
out on FSX pin.
12.9.16.1 Other Considerations
If the sample rate generator creates a frame-synchronization signal (FSG) that is derived from an external
input clock, the GSYNC bit determines whether FSG is kept synchronized with pulses on the FSR pin. For
more details, see Section 12.4.3.
In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave in the SPI
protocol. If the McBSP is a master and must provide a slave-enable signal (SPISTE) on the FSX pin,
make sure that FSXM = 1 and FSGM = 0 so that FSX is an output and is driven active for the duration of
each transmission. If the McBSP is a slave, make sure that FSXM = 0 so that the McBSP can receive the
slave-enable signal on the FSX pin.
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