Configuring XBANK Cycles
www.ti.com
850
SPRUI07–March 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
External Interface (XINTF)
14.5 Configuring XBANK Cycles
When jumping from one XINTF zone to another XINTF zone, a slow device may require extra cycles in
order to release the bus in time for another device to gain access. Bank switching allows the XINTF to add
extra cycles for any access that crosses into or out of the specified zone. The zone and number of cycles
is configured in the XBANK register.
Select the number of delay cycles based on the ratio of XTIMCLK and XCLKOUT. There are three cases:
• Case 1: XTIMCLK = SYSCLKOUT
When XTIMCLK is equal to SYSCLKOUT, there are no restrictions on the selection of XBANK[BCYC].
• Case 2: XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = 1/2 XTIMCLK
In this case, XBANK[BCYC] must not be 4 or 6. Any other value is valid.
• Case 3: XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = XTIMCLK
• Case 4: XTIMCLK = 1/4 SYSCLKOUT
When delay cycles are inserted between two accesses, there is a zone access before the delay cycles
and a zone access after the delay cycles. In order for bank switching to correctly insert the correct
number of delay cycles the total access time to the first zone in the sequence must be greater than the
number of bank cycles specified. To make sure this happens select XBANK[BCYC] such that it is
smaller than the total access to the zone.
Consider this example: Bank switching is enabled for Zone 7 (XBANK[BANK] = 7) . Delay cycles will
be added to any access into or out of Zone 7. This means:
– If an access to Zone 0 is followed by Zone 7
The access to Zone 0 must be longer than the number of bank cycles specified.
– If an access to Zone 1 is followed by Zone 7
The access to Zone 1must be longer than the number of bank cycles specified.
– If an access to Zone 7 is followed by Zone 0:
The access to Zone 7 must be longer than the number of bank cycles specified.
The lead, active and trail values can be used to make sure the access time is longer than the number
of delay cycles. Since XREADY can only extend the access longer, it need not be considered.
If X2TIMING is 0, then select:
– XBANK[BCYC] < XWRLEAD + XWRACTIVE + 1 + XWRTRAIL and
– XBANK[BCYC] < XRDLEAD + XRDACTIVE + 1 + XRDTRAIL
If X2TIMING = 1, then select:
– XBANK[BCYC] < XWRLEADx2 + XWRACTIVEx2 + 1 + XWRTRAILx2 and
– XBANK[BCYC] < XRDLEADx2 + XRDACTIVEx2 + 1 + XRDTRAILx2
Table 14-6 lists valid XBANK[BCYC] values for different timing configurations. The lead, active and trail
values are specified in the zones XTIMING register. When determining the proper XBANK[BCYC] values,
use the timing that yields the longest access time. This may be the read or the write timing.
Table 14-6. Valid XBANK Configurations
Valid XBANK[BCYC] Total Access Time XRDLEAD or
XWRLEAD
XRDACTIVE or
XWRACTIVE
XRDTRAIL or
XWRTRAIL
X2TIMING
< 5 1 + (2+1) + 1 = 5 1 2 1 0
< 6 1 + (3+1) + 1 = 6 1 3 1 0
< 7 2 + (3+1) + 1 = 7 2 3 1 0
< 5 1x2 + 0x2 + 1 + 1x2 1 0 1 1
< 5 1x2 + 1x2 + 1 + 0x2 1 1 0 1
To Next Page
Loading...
Need help?
General
