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eCAP Registers
373
SPRUI07–March 2020
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Enhanced Capture (eCAP)
5.8.2.1 TSCTR Register (Offset = 0h) [reset = 0h]
TSCTR is shown in Figure 5-18 and described in Table 5-4.
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Time-Stamp Counter
Figure 5-18. TSCTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSCTR
R/W-0h
Table 5-4. TSCTR Register Field Descriptions
Bit Field Type Reset Description
31-0 TSCTR R/W 0h
Active 32-bit counter register that is used as the capture time-base
Reset type: SYSRSn
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